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From:   "Chevron Li (WH)" <chevron.li@bayhubtech.com>
To:     "adrian.hunter@intel.com" <adrian.hunter@intel.com>,
        "ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
        "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "Shirley Her(SC)" <shirley.her@bayhubtech.com>,
        "XiaoGuang Yu (WH)" <xiaoguang.yu@bayhubtech.com>,
        "Shaper Liu (WH)" <shaper.liu@bayhubtech.com>,
        "Justin Wang (WH)" <justin.wang@bayhubtech.com>,
        Chevron Li <chevron_li@126.com>
Subject: RE: [PATCH V1 1/1] mmc: sdhci: fix DMA configure compatibility issue
 when 64bit DMA mode is used.
Thread-Topic: [PATCH V1 1/1] mmc: sdhci: fix DMA configure compatibility issue
 when 64bit DMA mode is used.
Thread-Index: AQHZjWdihWBVzy0abUm9tKKNGHDpg69xMEgA
Date:   Mon, 29 May 2023 12:07:55 +0000
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References: <20230523111114.18124-1-chevron_li@126.com>
In-Reply-To: <20230523111114.18124-1-chevron_li@126.com>
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Hi, Adrian/Ulf,

May I know the patch progress?
Look forward your response.

BR,
Chevron

-----Original Message-----
From: Chevron Li <chevron_li@126.com>=20
Sent: Tuesday, May 23, 2023 19:11
To: adrian.hunter@intel.com; ulf.hansson@linaro.org; linux-mmc@vger.kernel.=
org; linux-kernel@vger.kernel.org
Cc: Shirley Her(SC) <shirley.her@bayhubtech.com>; XiaoGuang Yu (WH) <xiaogu=
ang.yu@bayhubtech.com>; Shaper Liu (WH) <shaper.liu@bayhubtech.com>; Justin=
 Wang (WH) <justin.wang@bayhubtech.com>; Chevron Li (WH) <chevron.li@bayhub=
tech.com>
Subject: [PATCH V1 1/1] mmc: sdhci: fix DMA configure compatibility issue w=
hen 64bit DMA mode is used.

From: Chevron Li <chevron.li@bayhubtech.com>

Bayhub SD host has hardware limitation:
1.The upper 32bit address is inhibited to be written at SD Host Register
  [03E][13]=3D0 (32bits addressing) mode, is admitted to be written only at
  SD Host Register [03E][13]=3D1 (64bits addressing) mode.
2.Because of above item#1, need to configure SD Host Register [03E][13] to
  1(64bits addressing mode) before set 64bit ADMA system address's higher
  32bits SD Host Register [05F~05C] if 64 bits addressing mode is used.

The hardware limitation is reasonable for below reasons:
1.Normal flow should set DMA working mode first, then do
  DMA-transfer-related configuration, such as system address.
2.The hardware limitation may avoid the software to configure wrong higher
  32bit address at 32bits addressing mode although it is redundant.

The change that set 32bits/64bits addressing mode before set ADMA address,
  has no side-effect to other host IPs for below reason:
The setting order is reasonable and standard: DMA Mode setting first and
  then DMA address setting. It meets all DMA setting sequence.

Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>
---
Change in V1:
Set dma mode configure before set dma address
---
 drivers/mmc/host/sdhci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 3241=
916141d7..ff41aa56564e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1167,6 +1167,8 @@ static void sdhci_prepare_data(struct sdhci_host *hos=
t, struct mmc_command *cmd)
 		}
 	}
=20
+	sdhci_config_dma(host);
+
 	if (host->flags & SDHCI_REQ_USE_DMA) {
 		int sg_cnt =3D sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
=20
@@ -1186,8 +1188,6 @@ static void sdhci_prepare_data(struct sdhci_host *hos=
t, struct mmc_command *cmd)
 		}
 	}
=20
-	sdhci_config_dma(host);
-
 	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 		int flags;
=20

base-commit: cc3c44c9fda264c6d401be04e95449a57c1231c6
--
2.25.1