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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Mon, 29 May 2023 22:41:31 +0200
Message-ID: <CAFBinCCk6OziOxt2AY1A25C=9_pibhHsDK0wJNZ_AyHMd=z6SQ@mail.gmail.com>
Subject: Re: [PATCH v1] meson saradc: fix clock divider mask length
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Hi George,

On Mon, May 22, 2023 at 5:47=E2=80=AFPM =D0=A1=D1=82=D0=B0=D1=80=D0=BA =D0=
=93=D0=B5=D0=BE=D1=80=D0=B3=D0=B8=D0=B9 =D0=9D=D0=B8=D0=BA=D0=BE=D0=BB=D0=
=B0=D0=B5=D0=B2=D0=B8=D1=87
<GNStark@sberdevices.ru> wrote:
>
> Hello Martin
>
> Actually you were right that my patch affects only meson8 family not the =
all new ones, my bad.
> It's clear from the driver code meson_saradc.c and dts files.
> I've made an experiment on a113l soc - changingclock_rate inmeson_sar_adc=
_param and measuring adc channel many times
> and with low clockfrequency (priv->adc_clk) time of measurementis high
> and vice versa. ADC_CLK_DIV field in SAR_ADC_REG3 is always zero.
Thanks for sharing your findings!

> I need to get s805 (meson8) board for example and made experiment on it.
If you don't find any Meson8 (S802)/Meson8b (S805) or Meson8m2 (S812)
board then please provide the code that you used for your experiment
as a patch so I can give it a try on my Odroid-C1 (Meson8b).


Best regards,
Martin