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Message-ID: <dd4b1867-204d-8ee0-fcfc-29c52abddb48@kernel.org>
Date:   Tue, 30 May 2023 08:37:07 +0900
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Subject: Re: [PATCH v4 7/7] PCI: endpoint: Add PCI Endpoint function driver
 for MHI bus
To:     Manivannan Sadhasivam <mani@kernel.org>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        kw@linux.com, kishon@kernel.org, bhelgaas@google.com,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-msm@vger.kernel.org
References: <20230519144215.25167-1-manivannan.sadhasivam@linaro.org>
 <20230519144215.25167-8-manivannan.sadhasivam@linaro.org>
 <ZHSkdakXJegKRD+q@lpieralisi> <20230529173815.GG5633@thinkpad>
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From:   Damien Le Moal <dlemoal@kernel.org>
Organization: Western Digital Research
In-Reply-To: <20230529173815.GG5633@thinkpad>
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On 5/30/23 02:38, Manivannan Sadhasivam wrote:
[...]
>>> +static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr,
>>> +				   phys_addr_t phys_addr, void __iomem *virt_addr, size_t size)
>>> +{
>>> +	struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl);
>>> +	struct pci_epf *epf = epf_mhi->epf;
>>> +	struct pci_epc *epc = epf->epc;
>>> +	size_t offset = pci_addr & (epc->mem->window.page_size - 1);
>>> +
>>> +	pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr - offset);
>>> +	pci_epc_mem_free_addr(epc, phys_addr - offset, virt_addr - offset, size + offset);
>>> +}
>>> +
>>> +static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector)
>>> +{
>>> +	struct pci_epf_mhi *epf_mhi = container_of(mhi_cntrl, struct pci_epf_mhi, mhi_cntrl);
>>> +	struct pci_epf *epf = epf_mhi->epf;
>>> +	struct pci_epc *epc = epf->epc;
>>> +
>>> +	/*
>>> +	 * Vector is incremented by 1 here as the DWC core will decrement it before
>>> +	 * writing to iATU.
>>
>> This isn't OK. It is an API, you can't write code explicitly relying on
>> the underlying implementation. I assume the API is not well specified,
>> that's why we need these tricks ?
>>
> 
> Well, this is not an API issue but rather an implementation detail of the DWC EP
> core driver. The DWC driver expects the interrupt vectors to be 1 based, so it
> decrements it before writing to the MSI address:
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-designware-ep.c#n537

Then the driver should be fixed so that this peculiarity is not visible at the
user API level, resulting in a uniform usage of the API for all functions
regardless of the controller being used.

-- 
Damien Le Moal
Western Digital Research