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drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); - max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; + max_vblank_mallregion = max(drr_stretched_vblank_us, mall_region_us); /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis @@ -1008,7 +1008,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; subvp_active_us = main_timing->v_addressable * main_timing->h_total / (double)(main_timing->pix_clk_100hz * 100) * 1000000; - max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; + max_vblank_mallregion = max(vblank_blank_us, mall_region_us); // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, // and the max of (VBLANK blanking time, MALL region) -- 2.39.0