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Date:   Tue, 30 May 2023 09:03:32 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@orcam.me.uk>
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Paul Cercueil <paul@crapouillou.net>
cc:     linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Subject: Re: [PATCH 1/2] MIPS: Allow MIPS32R2 kernel to run on P5600 and
 M5150
In-Reply-To: <20230529135245.4085-1-jiaxun.yang@flygoat.com>
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References: <20230529135245.4085-1-jiaxun.yang@flygoat.com>
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On Mon, 29 May 2023, Jiaxun Yang wrote:

> M5150 and P5600 are two MIPS32R5 kernels, however as MIPS32R5 is
> backward compatible with MIPS32R2 there is no reason to forbid
> M5150 and P5600 on MIPS32R2 kernel.

 What problem are you trying to solve?  The CONFIG_SYS_HAS_CPU_* settings 
denote overall platform's support for the given CPU and have nothing to do 
with what architecture level a given kernel has been configured for.  You 
do need to get the settings right for your platform, just as you do in 
2/2, but this 1/2 part looks wrong to me.

 NB CPU_4KEC is double-listed as R1 and R2 because early revisions of the 
4KEc core were actually R1 before switching to R2, so this CPU can report 
either revision.

 I don't know why CPU_XBURST is also listed as both R1 and R2, the history 
looks convoluted with no explanation.  Paul, is the CPU also dual-revision 
or is it just a bug and it is supposed to be listed under one ISA revision
only, presumably R2?

  Maciej