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[209.85.219.170]) by smtp.gmail.com with ESMTPSA id g74-20020a0ddd4d000000b00565b26a9c9csm3468008ywe.64.2023.05.30.01.13.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 May 2023 01:13:35 -0700 (PDT) Received: by mail-yb1-f170.google.com with SMTP id 3f1490d57ef6-ba8afcc82c0so7723002276.2; Tue, 30 May 2023 01:13:35 -0700 (PDT) X-Received: by 2002:a25:cf96:0:b0:bad:f1f:7d4b with SMTP id f144-20020a25cf96000000b00bad0f1f7d4bmr1994288ybg.24.1685434415493; Tue, 30 May 2023 01:13:35 -0700 (PDT) MIME-Version: 1.0 References: <20220307143014.22758-1-lcherian@marvell.com> <164668950224.3277206.2552145973830842260.b4-ty@kernel.org> In-Reply-To: <164668950224.3277206.2552145973830842260.b4-ty@kernel.org> From: Geert Uytterhoeven Date: Tue, 30 May 2023 10:13:23 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR To: Will Deacon Cc: catalin.marinas@arm.com, Linu Cherian , maz@kernel.org, tglx@linutronix.de, kernel-team@android.com, linuc.decode@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linux-Renesas Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, On Mon, Mar 7, 2022 at 11:15 PM Will Deacon wrote: > On Mon, 7 Mar 2022 20:00:14 +0530, Linu Cherian wrote: > > When a IAR register read races with a GIC interrupt RELEASE event, > > GIC-CPU interface could wrongly return a valid INTID to the CPU > > for an interrupt that is already released(non activated) instead of 0x3ff. > > > > As a side effect, an interrupt handler could run twice, once with > > interrupt priority and then with idle priority. > > > > [...] > > Applied to arm64 (for-next/errata), thanks! > > [1/1] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR > https://git.kernel.org/arm64/c/24a147bcef8c This workaround is now enabled on R-Car V4H: GIC: enabling workaround for GICv3: Cavium erratum 38539 which is not a Cavium SoC. Is this expected? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds