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bh=rUslCAqAUHYdcANPf4Fjrc2wg7fzvi8y+ZTvGo2i9IM=; b=JMbIKyF6+sWF1rlTCsPkD9x/IqiNgF9nV9UY5EjcwK1OYxdRrbsVp59ex22OmBo2C7 K0Kq2/tpdfPRNPRAv73VvhdeEwJ74Ol5BqEWn7PV1Qmsbf+Ai9TIanb9i8snFGwzp/S+ oUqvytLW5KaBqn4J6SJO4Kj61rUoZ8tunvR045LXLe8NZtMZFQ8vq3BC5hBrFMpIe764 j3aw81Ub5Htd/Ln0bh4YpAtZQSQnw9ZERkSNyIdXYLZihHvx/MFR9rIHpl1ZtEdyPnd6 ZFOZ8b4RlTWtP/qQ39EfOUo83tG1oVrsiPKWFjIsd0y6GJu2QlsTWCgHWCxPg7JKdzbl zwWg== X-Gm-Message-State: AC+VfDxKvFpfQIbYFxy+9wVx0LPcsepXNH/wE8YTDrKJmsJDcWVxCAON p4WuSZmCt2zaq8fJFKz415CIzUSoCQf17Xq6YH0= X-Received: by 2002:aca:bf86:0:b0:39a:4170:6840 with SMTP id p128-20020acabf86000000b0039a41706840mr83300oif.21.1685434761311; Tue, 30 May 2023 01:19:21 -0700 (PDT) MIME-Version: 1.0 References: <20230427055032.85015-1-rath@ibv-augsburg.de> <20230427055032.85015-2-rath@ibv-augsburg.de> In-Reply-To: <20230427055032.85015-2-rath@ibv-augsburg.de> From: Christian Gmeiner Date: Tue, 30 May 2023 10:19:10 +0200 Message-ID: Subject: Re: [PATCH v2 1/3] dt-bindings: phy: cadence-torrent: Add latency properties To: Dominic Rath Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tjoseph@cadence.com, bhelgaas@google.com, lpieralisi@kernel.org, nm@ti.com, vigneshr@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, bahle@ibv-augsburg.de Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > From: Alexander Bahle > > Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for > setting the PCIe PHY latencies. > The properties expect a list of uint32 PHY latencies in picoseconds for > every supported speed starting at PCIe Gen1, e.g.: > > tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ > rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ > > Signed-off-by: Alexander Bahle > Signed-off-by: Dominic Rath Reviewed-by: Christian Gmeiner > --- > .../bindings/phy/phy-cadence-torrent.yaml | 20 +++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml > index 2ad1faadda2a..93228a304395 100644 > --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml > @@ -126,6 +126,24 @@ patternProperties: > enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100] > default: 8100 > > + tx-phy-latency-ps: > + description: > + The PHY latencies for the TX direction applied to PCIe PTM timestamps. Most > + PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain > + accurate PTM timestamps, the PCIe PTM specification requires that the time > + at which the first serial bit is present on the serial lines be taken. > + Should contain picosecond latency values for each supported speed, > + starting with Gen1 latency. > + > + rx-phy-latency-ps: > + description: > + The PHY latencies for the RX direction applied to the PTM timestamps. Most > + PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain > + accurate PTM timestamps, the PCIe PTM specification requires that the time > + at which the first serial bit is present on the serial lines be taken. > + Should contain picosecond latency values for each supported speed, > + starting with Gen1 latency. > + > required: > - reg > - resets > @@ -203,6 +221,8 @@ examples: > cdns,phy-type = ; > cdns,num-lanes = <2>; > cdns,ssc-mode = ; > + tx-phy-latency-ps = <138800 69400>; > + rx-phy-latency-ps = <185200 92600>; > }; > > phy@2 { > -- > 2.36.0 > -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy