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References: <20230427055032.85015-1-rath@ibv-augsburg.de> <20230427055032.85015-2-rath@ibv-augsburg.de>
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From:   Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue, 30 May 2023 10:19:10 +0200
Message-ID: <CAH9NwWfcjKw_e1qjo7bOPwjipfzVVVNh=9JEbB5Z+XAr6edd9w@mail.gmail.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: phy: cadence-torrent: Add latency properties
To:     Dominic Rath <rath@ibv-augsburg.de>
Cc:     robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        tjoseph@cadence.com, bhelgaas@google.com, lpieralisi@kernel.org,
        nm@ti.com, vigneshr@ti.com, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
        bahle@ibv-augsburg.de
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>
> From: Alexander Bahle <bahle@ibv-augsburg.de>
>
> Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for
> setting the PCIe PHY latencies.
> The properties expect a list of uint32 PHY latencies in picoseconds for
> every supported speed starting at PCIe Gen1, e.g.:
>
>   tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */
>   rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */
>
> Signed-off-by: Alexander Bahle <bahle@ibv-augsburg.de>
> Signed-off-by: Dominic Rath <rath@ibv-augsburg.de>

Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

> ---
>  .../bindings/phy/phy-cadence-torrent.yaml     | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 2ad1faadda2a..93228a304395 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -126,6 +126,24 @@ patternProperties:
>          enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
>          default: 8100
>
> +      tx-phy-latency-ps:
> +        description:
> +          The PHY latencies for the TX direction applied to PCIe PTM timestamps. Most
> +          PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
> +          accurate PTM timestamps, the PCIe PTM specification requires that the time
> +          at which the first serial bit is present on the serial lines be taken.
> +          Should contain picosecond latency values for each supported speed,
> +          starting with Gen1 latency.
> +
> +      rx-phy-latency-ps:
> +        description:
> +          The PHY latencies for the RX direction applied to the PTM timestamps. Most
> +          PCIe PHYs have asynchronous latencies for their RX and TX paths. To obtain
> +          accurate PTM timestamps, the PCIe PTM specification requires that the time
> +          at which the first serial bit is present on the serial lines be taken.
> +          Should contain picosecond latency values for each supported speed,
> +          starting with Gen1 latency.
> +
>      required:
>        - reg
>        - resets
> @@ -203,6 +221,8 @@ examples:
>                  cdns,phy-type = <PHY_TYPE_PCIE>;
>                  cdns,num-lanes = <2>;
>                  cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
> +                tx-phy-latency-ps = <138800 69400>;
> +                rx-phy-latency-ps = <185200 92600>;
>              };
>
>              phy@2 {
> --
> 2.36.0
>


-- 
greets
--
Christian Gmeiner, MSc

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