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Message-ID: <45a42e25658393e3767071960214b0ff47f0737b.camel@crapouillou.net>
Subject: Re: [PATCH 1/2] MIPS: Allow MIPS32R2 kernel to run on P5600 and
 M5150
From:   Paul Cercueil <paul@crapouillou.net>
To:     "Maciej W. Rozycki" <macro@orcam.me.uk>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc:     linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date:   Tue, 30 May 2023 11:18:56 +0300
In-Reply-To: <alpine.DEB.2.21.2305300321520.25569@angie.orcam.me.uk>
References: <20230529135245.4085-1-jiaxun.yang@flygoat.com>
         <alpine.DEB.2.21.2305300321520.25569@angie.orcam.me.uk>
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Hi Maciej,

Le mardi 30 mai 2023 =C3=A0 09:03 +0100, Maciej W. Rozycki a =C3=A9crit=C2=
=A0:
> On Mon, 29 May 2023, Jiaxun Yang wrote:
>=20
> > M5150 and P5600 are two MIPS32R5 kernels, however as MIPS32R5 is
> > backward compatible with MIPS32R2 there is no reason to forbid
> > M5150 and P5600 on MIPS32R2 kernel.
>=20
> =C2=A0What problem are you trying to solve?=C2=A0 The CONFIG_SYS_HAS_CPU_=
*
> settings=20
> denote overall platform's support for the given CPU and have nothing
> to do=20
> with what architecture level a given kernel has been configured for.=C2=
=A0
> You=20
> do need to get the settings right for your platform, just as you do
> in=20
> 2/2, but this 1/2 part looks wrong to me.
>=20
> =C2=A0NB CPU_4KEC is double-listed as R1 and R2 because early revisions o=
f
> the=20
> 4KEc core were actually R1 before switching to R2, so this CPU can
> report=20
> either revision.
>=20
> =C2=A0I don't know why CPU_XBURST is also listed as both R1 and R2, the
> history=20
> looks convoluted with no explanation.=C2=A0 Paul, is the CPU also dual-
> revision=20
> or is it just a bug and it is supposed to be listed under one ISA
> revision
> only, presumably R2?

The XBurst CPU is R1 in older Ingenic SoCs (JZ4760B and older), and R2
in newer SoCs (JZ4770 and newer).

Cheers,
-Paul