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Date:   Tue, 30 May 2023 10:13:47 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@orcam.me.uk>
To:     Paul Cercueil <paul@crapouillou.net>
cc:     Jiaxun Yang <jiaxun.yang@flygoat.com>, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Subject: Re: [PATCH 1/2] MIPS: Allow MIPS32R2 kernel to run on P5600 and
 M5150
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Hi Paul,

> >  I don't know why CPU_XBURST is also listed as both R1 and R2, the
> > history 
> > looks convoluted with no explanation.  Paul, is the CPU also dual-
> > revision 
> > or is it just a bug and it is supposed to be listed under one ISA
> > revision
> > only, presumably R2?
> 
> The XBurst CPU is R1 in older Ingenic SoCs (JZ4760B and older), and R2
> in newer SoCs (JZ4770 and newer).

 Great, thanks for confirming.  So the current arrangement is right and 
still we don't want to dual-list the P5600 or M5150.

  Maciej