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[209.85.219.181]) by smtp.gmail.com with ESMTPSA id o15-20020a81de4f000000b00568bc0bbf8esm619116ywl.71.2023.05.30.02.58.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 May 2023 02:58:47 -0700 (PDT) Received: by mail-yb1-f181.google.com with SMTP id 3f1490d57ef6-ba829e17aacso6031913276.0; Tue, 30 May 2023 02:58:47 -0700 (PDT) X-Received: by 2002:a25:1585:0:b0:b9e:7ec8:5d45 with SMTP id 127-20020a251585000000b00b9e7ec85d45mr1954396ybv.55.1685440727022; Tue, 30 May 2023 02:58:47 -0700 (PDT) MIME-Version: 1.0 References: <20230515131353.v2.cover@dianders> <20230515131353.v2.2.I88dc0a0eb1d9d537de61604cd8994ecc55c0cac1@changeid> <868rd6cfsy.wl-maz@kernel.org> In-Reply-To: <868rd6cfsy.wl-maz@kernel.org> From: Geert Uytterhoeven Date: Tue, 30 May 2023 11:58:34 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/5] irqchip/gic-v3: Disable pseudo NMIs on Mediatek devices w/ firmware issues To: Marc Zyngier Cc: Douglas Anderson , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Allen-KH Cheng , linux-mediatek@lists.infradead.org, Eddie Huang , Hsin-Hsiung Wang , AngeloGioacchino Del Regno , wenst@chromium.org, yidilin@chromium.org, Tinghan Shen , jwerner@chromium.org, Weiyi Lu , Ben Ho , Seiya Wang , linux-kernel@vger.kernel.org, Linux-Renesas Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On Tue, May 30, 2023 at 11:46 AM Marc Zyngier wrote: > On Tue, 30 May 2023 09:29:02 +0100, > Geert Uytterhoeven wrote: > > On Mon, May 15, 2023 at 10:16 PM Douglas Anderson wrote: > > > Some Chromebooks with Mediatek SoCs have a problem where the firmware > > > doesn't properly save/restore certain GICR registers. Newer > > > Chromebooks should fix this issue and we may be able to do firmware > > > updates for old Chromebooks. At the moment, the only known issue with > > > these Chromebooks is that we can't enable "pseudo NMIs" since the > > > priority register can be lost. Enabling "pseudo NMIs" on Chromebooks > > > with the problematic firmware causes crashes and freezes. > > > > > > Let's detect devices with this problem and then disable "pseudo NMIs" > > > on them. We'll detect the problem by looking for the presence of the > > > "mediatek,broken-save-restore-fw" property in the GIC device tree > > > node. Any devices with fixed firmware will not have this property. > > > > > > Our detection plan works because we never bake a Chromebook's device > > > tree into firmware. Instead, device trees are always bundled with the > > > kernel. We'll update the device trees of all affected Chromebooks and > > > then we'll never enable "pseudo NMI" on a kernel that is bundled with > > > old device trees. When a firmware update is shipped that fixes this > > > issue it will know to patch the device tree to remove the property. > > > > > > In order to make this work, the quick detection mechanism of the GICv3 > > > code is extended to be able to look for properties in addition to > > > looking at "compatible". > > > > > > Reviewed-by: Julius Werner > > > Signed-off-by: Douglas Anderson > > > --- > > > > > > Changes in v2: > > > - mediatek,gicr-save-quirk => mediatek,broken-save-restore-fw > > > > Thanks for your patch, which is now commit 44bd78dd2b8897f5 > > ("irqchip/gic-v3: Disable pseudo NMIs on Mediatek devices w/ > > firmware issues") in v6.4-rc4. > > > > This causes enabling an unrelated workaround on R-Car V4H: > > > > GIC: enabling workaround for GICv3: Cavium erratum 38539 > > > > > --- a/drivers/irqchip/irq-gic-common.c > > > +++ b/drivers/irqchip/irq-gic-common.c > > > @@ -16,7 +16,11 @@ void gic_enable_of_quirks(const struct device_node *np, > > > const struct gic_quirk *quirks, void *data) > > > { > > > for (; quirks->desc; quirks++) { > > > - if (!of_device_is_compatible(np, quirks->compatible)) > > > + if (quirks->compatible && > > > + !of_device_is_compatible(np, quirks->compatible)) > > > + continue; > > > + if (quirks->property && > > > + !of_property_read_bool(np, quirks->property)) > > > continue; > > > > Presumably the loop should continue if none of quirks-compatible > > or quirks->property is set? > > Indeed, thanks for pointing that out. Can you give the following hack > a go (compile tested only)? > > diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c > index de47b51cdadb..7b591736ab58 100644 > --- a/drivers/irqchip/irq-gic-common.c > +++ b/drivers/irqchip/irq-gic-common.c > @@ -16,6 +16,8 @@ void gic_enable_of_quirks(const struct device_node *np, > const struct gic_quirk *quirks, void *data) > { > for (; quirks->desc; quirks++) { > + if (!quirks->compatible && !quirks->property) > + continue; > if (quirks->compatible && > !of_device_is_compatible(np, quirks->compatible)) > continue; > > If that works for you, I'll queue it ASAP. Thanks, that fixes the issue for me on Renesas White-Hawk (R-Car V4H). No regressions on Koelsch (R-Car M2-W) and Salvator-XS (R-Car H3 ES2.0). Tested-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds