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Subject: Re: [PATCH 1/2] MIPS: Allow MIPS32R2 kernel to run on P5600 and M5150
From:   Jiaxun Yang <jiaxun.yang@flygoat.com>
In-Reply-To: <alpine.DEB.2.21.2305300321520.25569@angie.orcam.me.uk>
Date:   Tue, 30 May 2023 11:11:46 +0100
Cc:     Paul Cercueil <paul@crapouillou.net>,
        "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        linux-kernel@vger.kernel.org,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Message-Id: <684C1A48-C743-4045-AF12-B0846FCE8EBE@flygoat.com>
References: <20230529135245.4085-1-jiaxun.yang@flygoat.com>
 <alpine.DEB.2.21.2305300321520.25569@angie.orcam.me.uk>
To:     "Maciej W. Rozycki" <macro@orcam.me.uk>
Precedence: bulk


> 2023=E5=B9=B45=E6=9C=8830=E6=97=A5 09:03=EF=BC=8CMaciej W. Rozycki =
<macro@orcam.me.uk> =E5=86=99=E9=81=93=EF=BC=9A
>=20
> On Mon, 29 May 2023, Jiaxun Yang wrote:
>=20
>> M5150 and P5600 are two MIPS32R5 kernels, however as MIPS32R5 is
>> backward compatible with MIPS32R2 there is no reason to forbid
>> M5150 and P5600 on MIPS32R2 kernel.
>=20
> What problem are you trying to solve?  The CONFIG_SYS_HAS_CPU_* =
settings=20
> denote overall platform's support for the given CPU and have nothing =
to do=20
> with what architecture level a given kernel has been configured for.  =
You=20
> do need to get the settings right for your platform, just as you do in=20=

> 2/2, but this 1/2 part looks wrong to me.

Well the universal target is to allow R2 generic kernel to run on R5 =
CPUs.
As R5 is backward compatible we can just have one universal kernel =
binary.

Allowing P5600 and M5150 to run on R2 kernel does not bring much =
overhead.
In fact only several bytes are added to kernel binary.

(Actually although M5150 is advertising as R5 it=E2=80=99s technically =
R2 because it does
not implement some features mandatory for R5.)

Thanks
- Jiaxun

>=20
> NB CPU_4KEC is double-listed as R1 and R2 because early revisions of =
the=20
> 4KEc core were actually R1 before switching to R2, so this CPU can =
report=20
> either revision.
>=20
> I don't know why CPU_XBURST is also listed as both R1 and R2, the =
history=20
> looks convoluted with no explanation.  Paul, is the CPU also =
dual-revision=20
> or is it just a bug and it is supposed to be listed under one ISA =
revision
> only, presumably R2?
>=20
>  Maciej