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Shutemov" Cc: LKML , x86@kernel.org, David Woodhouse , Andrew Cooper , Brian Gerst , Arjan van de Veen , Paolo Bonzini , Paul McKenney , Tom Lendacky , Sean Christopherson , Oleksandr Natalenko , Paul Menzel , "Guilherme G. Piccoli" , Piotr Gorski , Usama Arif , Juergen Gross , Boris Ostrovsky , xen-devel@lists.xenproject.org, Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Guo Ren , linux-csky@vger.kernel.org, Thomas Bogendoerfer , linux-mips@vger.kernel.org, "James E.J. Bottomley" , Helge Deller , linux-parisc@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, Mark Rutland , Sabin Rapan , "Michael Kelley (LINUX)" , Dave Hansen Subject: Re: [patch v3 31/36] x86/apic: Provide cpu_primary_thread mask In-Reply-To: <87mt1mjhk3.ffs@tglx> References: <20230508181633.089804905@linutronix.de> <20230508185218.962208640@linutronix.de> <20230524204818.3tjlwah2euncxzmh@box.shutemov.name> <87y1lbl7r6.ffs@tglx> <87sfbhlwp9.ffs@tglx> <20230529023939.mc2akptpxcg3eh2f@box.shutemov.name> <87bki3kkfi.ffs@tglx> <20230529203129.sthnhzgds7ynddxd@box.shutemov.name> <20230530005428.jyrc2ezx5raohlrt@box.shutemov.name> <87mt1mjhk3.ffs@tglx> Date: Tue, 30 May 2023 12:34:45 +0200 Message-ID: <87jzwqjeey.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 30 2023 at 11:26, Thomas Gleixner wrote: > On Tue, May 30 2023 at 03:54, Kirill A. Shutemov wrote: >> On Mon, May 29, 2023 at 11:31:29PM +0300, Kirill A. Shutemov wrote: >>> Disabling parallel bringup helps. I didn't look closer yet. If you have >>> an idea let me know. >> >> Okay, it crashes around .Lread_apicid due to touching MSRs that trigger #VE. >> >> Looks like the patch had no intention to enable parallel bringup on TDX. >> >> + * Intel-TDX has a secure RDMSR hypercall, but that needs to be >> + * implemented seperately in the low level startup ASM code. >> >> But CC_ATTR_GUEST_STATE_ENCRYPT that used to filter it out is >> SEV-ES-specific thingy and doesn't cover TDX. I don't think we have an >> attribute that fits nicely here. > > Bah. That sucks. Can we have something consistent in this CC space or needs everything to be extra magic per CC variant?