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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id m25-20020a2e97d9000000b002a8b9570403sm2866179ljj.31.2023.05.30.06.35.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 May 2023 06:35:11 -0700 (PDT) Message-ID: <1ceeb56e-3efd-6858-358a-bd1976c625b1@linaro.org> Date: Tue, 30 May 2023 15:35:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v8 01/18] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx Content-Language: en-US To: Krzysztof Kozlowski Cc: freedreno@lists.freedesktop.org, Sean Paul , Akhil P Oommen , devicetree@vger.kernel.org, Bjorn Andersson , Marijn Suijten , linux-arm-msm@vger.kernel.org, David Airlie , dri-devel@lists.freedesktop.org, Rob Clark , Abhinav Kumar , Conor Dooley , Daniel Vetter , Rob Clark , Konrad Dybcio , linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> <20230223-topic-gmuwrapper-v8-1-69c68206609e@linaro.org> <20230530122652.lct6tk6zseny6gxl@krzk-bin> From: Konrad Dybcio In-Reply-To: <20230530122652.lct6tk6zseny6gxl@krzk-bin> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30.05.2023 14:26, Krzysztof Kozlowski wrote: > On Mon, 29 May 2023 15:52:20 +0200, Konrad Dybcio wrote: >> The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks >> we'd normally assign to the GMU as if they were a part of the GMU, even >> though they are not". It's a (good) software representation of the GMU_CX >> and GMU_GX register spaces within the GPUSS that helps us programatically >> treat these de-facto GMU-less parts in a way that's very similar to their >> GMU-equipped cousins, massively saving up on code duplication. >> >> The "wrapper" register space was specifically designed to mimic the layout >> of a real GMU, though it rather obviously does not have the M3 core et al. >> >> GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be >> specified under the GPU node, just like their older cousins. Account >> for that. >> >> Signed-off-by: Konrad Dybcio >> --- >> .../devicetree/bindings/display/msm/gpu.yaml | 61 ++++++++++++++++++---- >> 1 file changed, 52 insertions(+), 9 deletions(-) >> > > Running 'make dtbs_check' with the schema in this patch gives the > following warnings. Consider if they are expected or the schema is > incorrect. These may not be new warnings. I think it'd be beneficial if the bot diffed the output of checks pre- and post- patch. Konrad > > Note that it is not yet a requirement to have 0 warnings for dtbs_check. > This will change in the future. > > Full log is available here: https://patchwork.ozlabs.org/patch/1787121 > > > gpu@2c00000: compatible: 'oneOf' conditional failed, one must be fixed: > arch/arm64/boot/dts/qcom/sm8150-hdk.dtb > arch/arm64/boot/dts/qcom/sm8150-mtp.dtb