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Date:   Tue, 30 May 2023 08:35:14 -0700
From:   Bjorn Andersson <quic_bjorande@quicinc.com>
To:     Manivannan Sadhasivam <mani@kernel.org>
CC:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Clark <robdclark@gmail.com>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        Sean Paul <sean@poorly.run>,
        Akhil P Oommen <quic_akhilpo@quicinc.com>,
        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
        <freedreno@lists.freedesktop.org>, <johan@kernel.org>
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
Message-ID: <20230530153514.GB3643653@hu-bjorande-lv.qualcomm.com>
References: <20230523011522.65351-1-quic_bjorande@quicinc.com>
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 <097944b0-fa7a-ad4d-1c3d-e74ab2b977de@linaro.org>
 <20230528170717.GG2814@thinkpad>
 <a64ac105-90cf-eea0-5cb2-74be201386a9@linaro.org>
 <20230529084614.GA5633@thinkpad>
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On Mon, May 29, 2023 at 02:16:14PM +0530, Manivannan Sadhasivam wrote:
> On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
> > On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> > >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > >>> From: Bjorn Andersson <bjorn.andersson@linaro.org>
[..]
> > >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
[..]
> > >>> +		gmu: gmu@3d6a000 {
[..]
> > >>> +			status = "disabled";
> > >> I've recently discovered that - and I am not 100% sure - all GMUs are
> > >> cache-coherent. Could you please ask somebody at qc about this?
> > >>
> > > 
> > > AFAIU, GMU's job is controlling the voltage and clock to the GPU.
> > Not just that, it's only the limited functionality we've implemented
> > upstream so far.
> > 
> 
> Okay, good to know!
> 
> > It doesn't do
> > > any data transactions on its own.
> > Of course it does. AP communication is done through MMIO writes and
> > the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
> > of the GPU registers (that nota bene don't have anything to do with
> > the GMU M3 core itself) lay within the GMU address space.
> > 

But those aren't shared memory accesses.

> 
> That doesn't justify the fact that cache coherency is needed, especially
> MMIO writes, unless GMU could snoop the MMIO writes to AP caches.
> 

In reviewing the downstream state again I noticed that the GPU smmu is
marked dma-coherent, so I will adjust that in v3.

Regards,
Bjorn