Received: by 2002:a05:6358:3188:b0:123:57c1:9b43 with SMTP id q8csp4793416rwd; Tue, 30 May 2023 09:58:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ47/PKMNFN3eYdETUzeVJPCv3e3dajmA4nqryNkiD++wyT8ixUOZfbdYZbUitfuv3VIqkuy X-Received: by 2002:a17:90a:e2d7:b0:24b:52cb:9a31 with SMTP id fr23-20020a17090ae2d700b0024b52cb9a31mr12116491pjb.22.1685465908896; Tue, 30 May 2023 09:58:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685465908; cv=none; d=google.com; s=arc-20160816; b=1DXCxgeKO2hYc2uPV2BZgZKBLhqLQo0U7yWIB9CBmtwAU4YZPuPKi1tBeZXGqbrlZr oHfEarkOTqbHFsOAu7k82INy4Rzxfa55Q+upScbC0c1NXpQus8yio5VGJi69DcP5psbf /Mq3E5yh7tmtn7MpIUbpMsbev4y7nILi/2UoKZuPCPzPlqpN0El56ltcxEFzUgXTH5fQ 1s0BrPNmtUtPuLxvQ2ZzJzADqI9XQi7HU8pwSQq8n35IjZiQOxayR7HKHNpblN125hYm JU8TVUBfkp0rsDA1oMSKksKa1d5YUDSujd47JgVawHwGN7io+BvrKUz3BVIJ9Sqn/7Xj 4qXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id; bh=+1q4n/PwYGfJi51pHad/aT0INNe8+vm2vhvgc/eaVDM=; b=0GoWFaWfqhgXe+sJa+FWofbnsNmwF/Cb6J7CUvzGKgq2AEu04zHRm1+qdl6L2o/WhS eYIhq65iiJzXwUCHrNCspsDFR/rzRA4ZPLaZ1s/Jh0wPU+kDz7LDFKDfhrM75S9gsky+ +S2WzH6JIutPC+ldPVQqb+N1vLa1mFWUm0hCQ1xHYDX6Dyi034/gw+SCSvp/cSGvO/wb Ox+NhrVcI5jTNTHbg/xIJPgDIaGHQf5dnbjO2H04VwKjGGkWcovuPaL93IkTfIJpPbVr TnvpoksMJqee08kLrE+HGqQpyfOlYfXad1T1q4TAa6JAaAo6BZFkb+txzkVWpPmTsZ86 DLjA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i1-20020a17090a65c100b002536c5eb7cfsi7325193pjs.58.2023.05.30.09.58.16; Tue, 30 May 2023 09:58:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232375AbjE3Qgk (ORCPT + 99 others); Tue, 30 May 2023 12:36:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231460AbjE3Qgi (ORCPT ); Tue, 30 May 2023 12:36:38 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1CED28F for ; Tue, 30 May 2023 09:36:28 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C3D816F2; Tue, 30 May 2023 09:37:13 -0700 (PDT) Received: from [10.1.34.168] (e126864.cambridge.arm.com [10.1.34.168]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 75F7D3F663; Tue, 30 May 2023 09:36:24 -0700 (PDT) Message-ID: <64701978-1b11-3dec-c0e4-57f1a0eee1fe@arm.com> Date: Tue, 30 May 2023 17:36:18 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 07/11] arm64: mops: handle MOPS exceptions Content-Language: en-US To: Colton Lewis Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Mark Brown , Luis Machado , Vladimir Murzin , linux-kernel@vger.kernel.org References: From: Kristina Martsenko In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/05/2023 20:50, Colton Lewis wrote: >> +    if (esr & ESR_ELx_MOPS_ISS_MEM_INST) { >> +        /* SET* instruction */ >> +        if (option_a ^ wrong_option) { >> +            /* Format is from Option A; forward set */ >> +            pt_regs_write_reg(regs, dstreg, dst + size); >> +            pt_regs_write_reg(regs, sizereg, -size); >> +        } >> +    } else { >> +        /* CPY* instruction */ >> +        if (!(option_a ^ wrong_option)) { >> +            /* Format is from Option B */ >> +            if (regs->pstate & PSR_N_BIT) { >> +                /* Backward copy */ >> +                pt_regs_write_reg(regs, dstreg, dst - size); >> +                pt_regs_write_reg(regs, srcreg, src - size); >> +            } >> +        } else { >> +            /* Format is from Option A */ >> +            if (size & BIT(63)) { >> +                /* Forward copy */ >> +                pt_regs_write_reg(regs, dstreg, dst + size); >> +                pt_regs_write_reg(regs, srcreg, src + size); >> +                pt_regs_write_reg(regs, sizereg, -size); >> +            } >> +        } >> +    } > > I can see an argument for styling things closely to the ARM manual as > you have done here, but Linux style recommends against deep nesting. In > this case it is unneeded. I believe this can be written as a single > if-else chain and that makes it easier to distinguish the three options. > > if ((esr & ESR_ELx_MOPS_ISS_MEM_INST) && (option_a ^ wrong_option)) { >     /* Format is from Option A; forward set */ >     pt_regs_write_reg(regs, dstreg, dst + size); >     pt_regs_write_reg(regs, sizereg, -size); > } else if ((option_a ^ wrong_option) && (size & BIT(63)) { >     /* Forward copy */ >     pt_regs_write_reg(regs, dstreg, dst + size); >     pt_regs_write_reg(regs, srcreg, src + size); >     pt_regs_write_reg(regs, sizereg, -size); > } else if (regs-pstate & PSR_N_BIT) { >     /* Backward copy */ >     pt_regs_write_reg(regs, dstreg, dst - size); >     pt_regs_write_reg(regs, srcreg, src - size); > } Yeah, the nesting gets a bit deep here, but there are 6 cases in total, ie 6 ways the hardware can set up the registers and pstate (in 3 of them the kernel doesn't need to modify the registers), and I think the current structure makes it clearer what the 6 are, so I'd prefer to keep it as it is for now. Thanks, Kristina