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[95.247.65.76]) by smtp.gmail.com with ESMTPSA id f6-20020a1709064dc600b0094f4d2d81d9sm7726268ejw.94.2023.05.30.11.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 11:45:33 -0700 (PDT) Date: Tue, 30 May 2023 20:45:28 +0200 From: Andrea Parri To: Palmer Dabbelt Cc: ajones@ventanamicro.com, heiko@sntech.de, linux-riscv@lists.infradead.org, Paul Walmsley , linux-kernel@vger.kernel.org, christoph.muellner@vrull.eu, David.Laight@aculab.com, heiko.stuebner@vrull.eu Subject: Re: [PATCH v3 2/2] riscv: Add Zawrs support for spinlocks Message-ID: References: <20230524-35efcabbbfd6a1ef83865fb4@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 24, 2023 at 04:00:43PM -0700, Palmer Dabbelt wrote: > On Wed, 24 May 2023 10:05:52 PDT (-0700), ajones@ventanamicro.com wrote: > > I guess this peeling off of the first iteration is because it's expected > > that the load generated by READ_ONCE() is more efficient than lr.w/d? If > > we're worried about unnecessary use of lr.w/d, then shouldn't we look > > for a solution that doesn't issue those instructions when we don't have > > the Zawrs extension? > > It's actually just a consequence of how the Linux hooks are described: > they're macros that take a C expression to test in the loop, and we can't > handle C expressions in LR/SC loops as that'd require compiler support and > nobody's figured out how to do that correctly yet (there were some patches, > but they had issues). So we need to do this awkward bit of checking without > the reservation and then waiting with the reservation. I believe Andrew was really just hinting to something like (from arch/arm64/): #define smp_cond_load_relaxed(ptr, cond_expr) \ ({ \ typeof(ptr) __PTR = (ptr); \ __unqual_scalar_typeof(*ptr) VAL; \ for (;;) { \ VAL = READ_ONCE(*__PTR); \ if (cond_expr) \ break; \ __cmpwait_relaxed(__PTR, VAL); \ } \ (typeof(*ptr))VAL; \ }) where the __cmpwait_relaxed() would issue NOPs without Zawrs, a sequence "lr.* ; beq ; wrs.sto" otherwise. (with the "dangling reservation" when we branch, similarly to CMPXCHG)? Andrea