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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x15-20020a17090ab00f00b002509203c8b2si11542968pjq.47.2023.05.30.15.53.25; Tue, 30 May 2023 15:53:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=google header.b=NuAS7EC5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233484AbjE3Wwt (ORCPT + 99 others); Tue, 30 May 2023 18:52:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233194AbjE3Wwo (ORCPT ); Tue, 30 May 2023 18:52:44 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDC6DEC for ; Tue, 30 May 2023 15:52:36 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-64d604cc0aaso4005604b3a.2 for ; Tue, 30 May 2023 15:52:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1685487156; x=1688079156; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=M3rAYjkkHYPU/OK4ZEufLlpPfAsJjD+qxWbkdRp2kH4=; b=NuAS7EC5qFf3tPtS0R8PRJY2szySViFSxr9yxEUWX0Gyn4yt/lMZq5AKeJ92nCsjBK S8ID2zsOHwHXMr358b1Ols09P1lDR5fyFRNSrW5t4Yev5k80OPWWuNBONEP2aNaU/x5Y RPhu1L3vIOCgCL0UcQN8e1boC5uu6qJc7Rk0Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685487156; x=1688079156; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=M3rAYjkkHYPU/OK4ZEufLlpPfAsJjD+qxWbkdRp2kH4=; b=ZIoom6Zd38VJLhvNAuZIVha866CbMFEF+qGUO9qpd9bT2MFBCcalIXbZVLrzJYA0Xa A5hb867uEOxCWGD2MTliEO6tGXikylgioY0NrjfgEh+ttnk7EHH7BvnN8B1bgvJv3VzA vP6E+OCzU904YxG2+g50+v4ALCaxiUJ5Rrm17PIh9/tPfc6Wd7wk+u1fGiYTwT7j08xm go9Z3doXB/TLLpF7p3OBxvNBAex7i6BgZwtla25DI1NzVCikXBpiAfMh+WVY2jbAA7vm cACE4xQgQKrn5AdABGSyrtpjbRNZECW3yxYpRPY+A+Oqv7d9eiJggGxSI5tn/0TbW2lh T+ow== X-Gm-Message-State: AC+VfDzLh/oTN2XjsVh07voAU/+KdHGqHslao6TcxpvR2zSJ8cz3k08O W9ohztBdVXWZmzQDK2cctwpLQQ== X-Received: by 2002:a17:903:644:b0:1af:babd:7b6d with SMTP id kh4-20020a170903064400b001afbabd7b6dmr3075052plb.52.1685487156127; Tue, 30 May 2023 15:52:36 -0700 (PDT) Received: from stbirv-lnx-3.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id s3-20020a170902b18300b001a1b66af22fsm10805011plr.62.2023.05.30.15.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 15:52:35 -0700 (PDT) From: Florian Fainelli To: stable@vger.kernel.org Cc: Pierre Gondois , Sudeep Holla , Florian Fainelli , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Akihiko Odaki , Palmer Dabbelt , Gavin Shan , Jeremy Linton , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH stable 6.3 1/4] cacheinfo: Add use_arch[|_cache]_info field/function Date: Tue, 30 May 2023 15:49:11 -0700 Message-Id: <20230530224914.1251409-2-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530224914.1251409-1-florian.fainelli@broadcom.com> References: <20230530224914.1251409-1-florian.fainelli@broadcom.com> MIME-Version: 1.0 Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="0000000000003cf91105fcf10f5b" X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0000000000003cf91105fcf10f5b Content-Transfer-Encoding: 8bit From: Pierre Gondois commit ef9f643a9f8b62bcbcc51f0e0af8599adc2e17ed upstream The cache information can be extracted from either a Device Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1 for arm64). The clidr_el1 register is used only if DT/ACPI information is not available. It does not states how caches are shared among CPUs. Add a use_arch_cache_info field/function to identify when the DT/ACPI doesn't provide cache information. Use this information to assume L1 caches are privates and L2 and higher are shared among all CPUs. Signed-off-by: Pierre Gondois Link: https://lore.kernel.org/r/20230414081453.244787-5-pierre.gondois@arm.com Signed-off-by: Sudeep Holla Signed-off-by: Florian Fainelli --- drivers/base/cacheinfo.c | 12 ++++++++++-- include/linux/cacheinfo.h | 6 ++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index ea8f416852bd..8120ac1ddbe4 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -28,6 +28,9 @@ static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cacheinfo); #define per_cpu_cacheinfo_idx(cpu, idx) \ (per_cpu_cacheinfo(cpu) + (idx)) +/* Set if no cache information is found in DT/ACPI. */ +static bool use_arch_info; + struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu) { return ci_cacheinfo(cpu); @@ -40,7 +43,8 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, * For non DT/ACPI systems, assume unique level 1 caches, * system-wide shared caches for all other levels. */ - if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) + if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)) || + use_arch_info) return (this_leaf->level != 1) && (sib_leaf->level != 1); if ((sib_leaf->attributes & CACHE_ID) && @@ -343,6 +347,10 @@ static int cache_setup_properties(unsigned int cpu) else if (!acpi_disabled) ret = cache_setup_acpi(cpu); + // Assume there is no cache information available in DT/ACPI from now. + if (ret && use_arch_cache_info()) + use_arch_info = true; + return ret; } @@ -361,7 +369,7 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) * to update the shared cpu_map if the cache attributes were * populated early before all the cpus are brought online */ - if (!last_level_cache_is_valid(cpu)) { + if (!last_level_cache_is_valid(cpu) && !use_arch_info) { ret = cache_setup_properties(cpu); if (ret) return ret; diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 908e19d17f49..b91cc9991c7c 100644 --- a/include/linux/cacheinfo.h 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