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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bs71-20020a63284a000000b005349009f1desi11599848pgb.354.2023.05.30.16.05.31; Tue, 30 May 2023 16:05:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b="SpDnqS/g"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232828AbjE3XAO (ORCPT + 99 others); Tue, 30 May 2023 19:00:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229794AbjE3XAN (ORCPT ); Tue, 30 May 2023 19:00:13 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89788EC; Tue, 30 May 2023 16:00:10 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-64d41d8bc63so4019806b3a.0; Tue, 30 May 2023 16:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685487610; x=1688079610; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=MhkmwhzVFv1bWKBw06RWKQ85zcFA8OuFNsMQdUaAwlA=; b=SpDnqS/gyx977+0QYAk/5vk8jfE9dMGQ/M551BHZsK8DyLDbQTZRbPNaqHbUTosgD6 08mbQ8xhC4Fy7Xw6nbGvifDdJKh7CngQLD9t/qNgpIP/JrBJA+be7GG2JNhe/X78KC/+ IAmI2BctwsmQcvJ3IZHLoqgL4ezJyvzZZ3eRN0AEMA1VgNAq3gF+FlSu7Ej7/Oi2VKsg TQ6K1prEtMK9KZnPn04boP7vhVdcrAYeKt55BCJvU1++ntA/fsjRi/NVyX7IUyY+E/G/ VjNYKh/QC1B6Fd9cBDkFfqTZHECT95nqNjikec+Dup1/yrhyNmEGQlnWn2lCWG7wwCyB RT8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685487610; x=1688079610; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=MhkmwhzVFv1bWKBw06RWKQ85zcFA8OuFNsMQdUaAwlA=; b=Ox2sLzwMTzelxYY/S33nPs9gUwyEywa0oij69SBV1HqbWesZHK2CzbMfd9pjsRqJQi u6P1hiu6tUhOBhvdwVyREdVxlvRccqNfhKEZdfw6Dl1IKnZARGE4eKN5pBSmr8JN913+ Isp161CjefT402JaXYeje8amc8hpYJwhX7rioYlVkRs8bMAKw+mDnctfe9c3n9z+8Odo +osuIh711a2RaDIqIMpMpLB9ugtmRbpva1yNF1BZ1mVmFPNw5q8yWO18LAVAwEPfCLvS +4YfkR5CpWg6C90nB8ob4o5DmpRJdVGKJ+sEXyjifFwb5b4bJjvdBcbyLY5h1tf52pNm zE0Q== X-Gm-Message-State: AC+VfDxG4Q0IkWnHxbLprtoorepqe7bi1uE2CKkI8cEx8H0WVt4sJECN NpOmbxPZopVxAPYFLh6Zj4Q= X-Received: by 2002:a05:6a21:6704:b0:10a:9f45:e3f with SMTP id wh4-20020a056a21670400b0010a9f450e3fmr3879785pzb.12.1685487609828; Tue, 30 May 2023 16:00:09 -0700 (PDT) Received: from localhost ([192.55.54.50]) by smtp.gmail.com with ESMTPSA id e2-20020a63ee02000000b00514256c05c2sm9445520pgi.7.2023.05.30.16.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 16:00:09 -0700 (PDT) Date: Tue, 30 May 2023 16:00:07 -0700 From: Isaku Yamahata To: Like Xu Cc: Isaku Yamahata , Zhi Wang , isaku.yamahata@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack , Kai Huang Subject: Re: [PATCH v13 021/113] KVM: TDX: Make pmu_intel.c ignore guest TD case Message-ID: <20230530230007.GF1234772@ls.amr.corp.intel.com> References: <017a06174fa054ae264a2caba6f7f55e00f258e8.1678643052.git.isaku.yamahata@intel.com> <20230402115019.000046fd@gmail.com> <36fb638a-c9ff-0139-3e8e-7e8ff0bbff1f@gmail.com> <20230528082602.GC1234772@ls.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 29, 2023 at 10:19:16PM +0800, Like Xu wrote: > On 28/5/2023 4:26 pm, Isaku Yamahata wrote: > > On Wed, Apr 19, 2023 at 04:21:21PM +0800, > > Like Xu wrote: > > > > > On 2/4/2023 4:50 pm, Zhi Wang wrote: > > > > Hi Like: > > > > > > > > Would you mind to take a look on this patch? It would be nice to have > > > > a r-b also from you. :) > > > > > > > > On Sun, 12 Mar 2023 10:55:45 -0700 > > > > isaku.yamahata@intel.com wrote: > > > > > > > > > From: Isaku Yamahata > > > > > > > > > > Because TDX KVM doesn't support PMU yet (it's future work of TDX KVM > > > > > support as another patch series) and pmu_intel.c touches vmx specific > > > > > > It would be nice to have pmu support for tdx-guest from the very beginning. > > > > It's supported in the public github repo. > > https://github.com/intel/tdx/tree/kvm-upstream-workaround > > As this patch series has 100+ patches, I don't want to bloat this patch more. > > I presume we are talking about 873e2391e729...63761adbf5aa for TD pmu: > > A quick glance brought me at least these comments: > > (1) how does intel_pmu_save/restore() handle the enabled host LBR/PEBS ? It's not handled yet. We need to save/restore those MSRs. > (2) guest PMI injection may be malicious and could the current guest pmu > driver handle it ? This isn't specific to PMI. Malicious VMM can inject any interrupt to the guest at any time. Guest should be prepared for it. > (3) how do we handle the case when host counters can be enabled before TDENTER > for debuggable TD and support the case like "perf-kvm for both guest and host" ? On TDEXIT, those are disabled. VMM has to restore MSRs and enable it again. There is a window where events can be missed. > My point is actually, changes to perf/core should be CC to the perf reviewers > as early as possible to prevent key player from killing the direction. Sure, agreed. > > > > > structure in vcpu initialization, as workaround add dummy structure to > > > > > struct vcpu_tdx and pmu_intel.c can ignore TDX case. > > > > > > If the target is not to provide a workaround, how about other variants: > > > - struct lbr_desc lbr_desc; > > > - pebs ds_buffer; > > > ? > > > > > > We also need tdx selftest to verify the unavailability of these features. > > > Also, it would be great to have TDX's "System Profiling Mode" featue back in > > > the specification. > > Detailed TD (plus debuggable) PMU selftest would clearly speed up the review > process. The existing KVM PMU selftest can be utilized. Or do you have something else in mind? -- Isaku Yamahata