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Date:   Wed, 31 May 2023 10:16:40 +0200
From:   Lukasz Majewski <lukma@denx.de>
To:     "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Vivien Didelot <vivien.didelot@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Vladimir Oltean <olteanv@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [RFC] net: dsa: slave: Advertise correct EEE capabilities at
 slave PHY setup
Message-ID: <20230531101640.131fe934@wsk>
In-Reply-To: <ZHYLNGkG26QP/QAS@shell.armlinux.org.uk>
References: <20230530122621.2142192-1-lukma@denx.de>
        <ZHXzTBOtlPKqNfLw@shell.armlinux.org.uk>
        <20230530160743.2c93a388@wsk>
        <ZHYGv7zcJd/Ad4hH@shell.armlinux.org.uk>
        <35546c34-17a6-4295-b263-3f2a97d53b94@lunn.ch>
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Hi Russell,

> On Tue, May 30, 2023 at 04:26:49PM +0200, Andrew Lunn wrote:
> > > So, I'm wondering what's actually going on here... can you give
> > > any more details about the hardware setup? =20
> >=20
> > And what switch it actually is. I've not looked in too much detail,
> > but i think different switch families have different EEE
> > capabilities. But in general, as Russell pointed out, there is no
> > MAC support for EEE in the mv88e6xxx driver. =20
>=20
> ... except for the built-in PHYs,

This is my case.

> which if they successfully negotiate
> EEE, that status is communicated back to the MAC in that one sees
> MV88E6352_PORT_STS_EEE

I cannot find this register in my documentation.

> set, which results in the MAC being able to
> signal LPI to the PHY... and I've stuck a 'scope on the PHY media-side
> signals in the past and have seen that activity does stop without
> there needing to be any help from the driver for this.
>=20
> At least reading the information I have for the 88E6352, there is no
> configuration of LPI timers, nor any seperate LPI enable. If EEE is
> enabled at the MAC, then LPI will be signalled according to whatever
> Marvell decided would be appropriate.

And this knowledge is not disclosed to public.

>=20
> For an external PHY that the PPU is not polling, the only way that
> we'd have EEE functional is if we forced EEE in port control register
> 1 on switches that support those bits. In other words setting both the
> EEE and FORCE_EEE bits...
>=20

Are those bits available in c45 standard? Or are they SoC (IC) specific?

In my case I do have only two c45 registers disclosed (i.e. described)
for mv88e6071 SoC in the documentation.


Best regards,

Lukasz Majewski

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