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References: <20230530095308.8165-1-victorshihgli@gmail.com>
 <20230530095308.8165-3-victorshihgli@gmail.com> <7c185eb3-5775-af7c-3035-2799e3395c33@intel.com>
In-Reply-To: <7c185eb3-5775-af7c-3035-2799e3395c33@intel.com>
From:   Victor Shih <victorshihgli@gmail.com>
Date:   Wed, 31 May 2023 17:45:31 +0800
Message-ID: <CAK00qKAn1WAh+zNT11L7G+fyGP-x0H7CzTFA3+T0GavpUufFVg@mail.gmail.com>
Subject: Re: [PATCH V2 2/3] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz
 and enable SSC for GL9767
To:     Adrian Hunter <adrian.hunter@intel.com>
Cc:     ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
        linux-kernel@vger.kernel.org, benchuanggli@gmail.com,
        HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw,
        Ben Chuang <ben.chuang@genesyslogic.com.tw>,
        Victor Shih <victor.shih@genesyslogic.com.tw>
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Hi, Adrian

On Wed, May 31, 2023 at 3:01=E2=80=AFPM Adrian Hunter <adrian.hunter@intel.=
com> wrote:
>
> On 30/05/23 12:53, Victor Shih wrote:
> > From: Victor Shih <victor.shih@genesyslogic.com.tw>
> >
> > Set GL9767 SDR104's clock to 205MHz and enable SSC feature
> > depend on register 0x888 BIT(1).
> >
> > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
> > ---
> >  drivers/mmc/host/sdhci-pci-gli.c | 135 ++++++++++++++++++++++++++++++-
> >  1 file changed, 134 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-=
pci-gli.c
> > index 3ed207b89d1a..178253a7e86f 100644
> > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > @@ -158,6 +158,12 @@
> >  #define   GLI_9767_VHS_REV_M   0x1
> >  #define   GLI_9767_VHS_REV_W   0x2
> >
> > +#define PCIE_GLI_9767_COM_MAILBOX            0x888
> > +#define   PCIE_GLI_9767_COM_MAILBOX_SSC_EN     BIT(1)
> > +
> > +#define PCIE_GLI_9767_CFG            0x8A0
> > +#define   PCIE_GLI_9767_CFG_LOW_PWR_OFF        BIT(12)
> > +
> >  #define PCIE_GLI_9767_PWR_MACRO_CTL                                  0=
x8D0
> >  #define   PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE                     =
 GENMASK(3, 0)
> >  #define   PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE          =
 GENMASK(15, 12)
> > @@ -175,6 +181,16 @@
> >  #define   PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF            BIT(21)
> >  #define   PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN     BIT(30)
> >
> > +#define PCIE_GLI_9767_SD_PLL_CTL                     0x938
> > +#define   PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV            GENMASK(9, 0)
> > +#define   PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV            GENMASK(15, 12)
> > +#define   PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN                  BIT(16)
> > +#define   PCIE_GLI_9767_SD_PLL_CTL_SSC_EN              BIT(19)
> > +#define   PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING    GENMASK(28, 24)
> > +
> > +#define PCIE_GLI_9767_SD_PLL_CTL2            0x93C
> > +#define   PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM         GENMASK(31, 16)
> > +
> >  #define GLI_MAX_TUNING_LOOP 40
> >
> >  /* Genesys Logic chipset */
> > @@ -753,6 +769,123 @@ static inline void gl9767_vhs_write(struct pci_de=
v *pdev)
> >       pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
> >  }
> >
> > +static bool gl9767_ssc_enable(struct pci_dev *pdev)
> > +{
> > +     u32 value;
> > +     u8 enable;
> > +
> > +     gl9767_vhs_write(pdev);
> > +
> > +     pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
> > +     enable =3D FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
> > +
> > +     gl9767_vhs_read(pdev);
> > +
> > +     return enable;
> > +}
> > +
> > +static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u=
16 ppm)
> > +{
> > +     u32 pll;
> > +     u32 ssc;
> > +
> > +     gl9767_vhs_write(pdev);
> > +
> > +     pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> > +     pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
> > +     pll &=3D ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
> > +              PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
> > +     ssc &=3D ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
> > +     pll |=3D FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, st=
ep) |
> > +            FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
> > +     ssc |=3D FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
> > +     pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
> > +     pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> > +
> > +     gl9767_vhs_read(pdev);
> > +}
> > +
> > +static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 =
pdiv)
> > +{
> > +     u32 pll;
> > +
> > +     gl9767_vhs_write(pdev);
> > +
> > +     pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> > +     pll &=3D ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
> > +              PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
> > +              PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
> > +     pll |=3D FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
> > +            FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
> > +            FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
> > +     pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> > +
> > +     gl9767_vhs_read(pdev);
> > +
> > +     /* wait for pll stable */
> > +     mdelay(1);
>
> So long as SDHCI_QUIRK_CLOCK_BEFORE_RESET is not used, it is OK
> to sleep here, so msleep() or usleep_range()
>

I will update it in patch v3.

> > +}
> > +
> > +static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
> > +{
> > +     bool enable =3D gl9767_ssc_enable(pdev);
> > +
> > +     /* set pll to 205MHz and ssc */
> > +     gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
> > +     gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
> > +}
> > +
> > +static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
> > +{
> > +     u32 pll;
> > +
> > +     gl9767_vhs_write(pdev);
> > +
> > +     pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> > +     pll &=3D ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD=
_PLL_CTL_SSC_EN);
> > +     pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> > +
> > +     gl9767_vhs_read(pdev);
> > +}
> > +
> > +static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned i=
nt clock)
> > +{
> > +     struct sdhci_pci_slot *slot =3D sdhci_priv(host);
> > +     struct mmc_ios *ios =3D &host->mmc->ios;
> > +     struct pci_dev *pdev;
> > +     u32 value;
> > +     u16 clk;
> > +
> > +     pdev =3D slot->chip->pdev;
> > +     host->mmc->actual_clock =3D 0;
> > +
> > +     gl9767_vhs_write(pdev);
> > +
> > +     pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> > +     value |=3D PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> > +     pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> > +
> > +     gl9767_disable_ssc_pll(pdev);
> > +     sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> > +
> > +     if (clock =3D=3D 0)
> > +             return;
> > +
> > +     clk =3D sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
> > +     if (clock =3D=3D 200000000 && ios->timing =3D=3D MMC_TIMING_UHS_S=
DR104) {
> > +             host->mmc->actual_clock =3D 205000000;
> > +             gl9767_set_ssc_pll_205mhz(pdev);
> > +     }
> > +
> > +     sdhci_enable_clk(host, clk);
> > +
> > +     pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> > +     value &=3D ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> > +     pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> > +
> > +     gl9767_vhs_read(pdev);
> > +}
> > +
> >  static void gli_set_9767(struct sdhci_host *host)
> >  {
> >       u32 value;
> > @@ -1293,7 +1426,7 @@ const struct sdhci_pci_fixes sdhci_gl9763e =3D {
> >  };
> >
> >  static const struct sdhci_ops sdhci_gl9767_ops =3D {
> > -     .set_clock               =3D sdhci_set_clock,
> > +     .set_clock               =3D sdhci_gl9767_set_clock,
> >       .enable_dma              =3D sdhci_pci_enable_dma,
> >       .set_bus_width           =3D sdhci_set_bus_width,
> >       .reset                   =3D sdhci_gl9767_reset,
>

Thanks, Victor Shih