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Message-ID: <da01a33d-a4f9-1086-3365-5a0528db16d9@linaro.org>
Date:   Wed, 31 May 2023 22:14:48 +0200
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Subject: Re: [PATCH v2 5/6] arm64: dts: qcom: sc8280xp: add resets for
 soundwire controllers
Content-Language: en-US
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
        andersson@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org
Cc:     johan+linaro@kernel.org, agross@kernel.org,
        mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20230525122930.17141-1-srinivas.kandagatla@linaro.org>
 <20230525122930.17141-6-srinivas.kandagatla@linaro.org>
 <542a67da-5870-dda0-3604-9367a438e51b@linaro.org>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <542a67da-5870-dda0-3604-9367a438e51b@linaro.org>
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On 31.05.2023 22:03, Krzysztof Kozlowski wrote:
> On 25/05/2023 14:29, Srinivas Kandagatla wrote:
>> Soundwire controllers on sc8280xp needs an explicit reset, add
>> support for this.
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 23 +++++++++++++++++++++++
>>  1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index 6730349e34f4..39be2e89ce05 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -6,6 +6,7 @@
>>  
>>  #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
>>  #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
>> +#include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h>
>>  #include <dt-bindings/clock/qcom,rpmh.h>
>>  #include <dt-bindings/interconnect/qcom,osm-l3.h>
>>  #include <dt-bindings/interconnect/qcom,sc8280xp.h>
>> @@ -2560,6 +2561,8 @@
>>  			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
>>  			clocks = <&rxmacro>;
>>  			clock-names = "iface";
>> +			resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
>> +			reset-names = "swr_audio_cgcr";
>>  			label = "RX";
>>  
>>  			qcom,din-ports = <0>;
>> @@ -2634,6 +2637,8 @@
>>  			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
>>  			clocks = <&wsamacro>;
>>  			clock-names = "iface";
>> +			resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
>> +			reset-names = "swr_audio_cgcr";
>>  			label = "WSA";
>>  
>>  			qcom,din-ports = <2>;
>> @@ -2656,6 +2661,14 @@
>>  			status = "disabled";
>>  		};
>>  
>> +		lpass_audiocc: clock-controller@32a9000 {
>> +			compatible = "qcom,sc8280xp-lpassaudiocc";
>> +			reg = <0 0x032a9000 0 0x1000>;
>> +			qcom,adsp-pil-mode;
> 
> Here and...
> 
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>>  		swr2: soundwire-controller@3330000 {
>>  			compatible = "qcom,soundwire-v1.6.0";
>>  			reg = <0 0x03330000 0 0x2000>;
>> @@ -2665,6 +2678,8 @@
>>  
>>  			clocks = <&txmacro>;
>>  			clock-names = "iface";
>> +			resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
>> +			reset-names = "swr_audio_cgcr";
>>  			label = "TX";
>>  			#sound-dai-cells = <1>;
>>  			#address-cells = <2>;
>> @@ -2901,6 +2916,14 @@
>>  			};
>>  		};
>>  
>> +		lpasscc: clock-controller@33e0000 {
>> +			compatible = "qcom,sc8280xp-lpasscc";
>> +			reg = <0 0x033e0000 0 0x12000>;
>> +			qcom,adsp-pil-mode;
> 
> ... here - where do you use these properties? Driver ignores them.
> 
> AFAIR, these were only for sc7280 where we supported two variants for audio.
Smells like pure copypasta - we don't support any 8280xp chromebooks (not
even sure if any exist) and WP devices have a normal TZ+PAS setup

Konrad
> 
> Best regards,
> Krzysztof
>