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Date:   Thu, 1 Jun 2023 14:07:50 +0100
From:   Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To:     Terry Bowman <terry.bowman@amd.com>
CC:     <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
        <ira.weiny@intel.com>, <bwidawsk@kernel.org>,
        <dan.j.williams@intel.com>, <dave.jiang@intel.com>,
        <linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
        <linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v4 12/23] cxl/pci: Store the endpoint's Component
 Register mappings in struct cxl_dev_state
Message-ID: <20230601140750.000006e6@Huawei.com>
In-Reply-To: <20230523232214.55282-13-terry.bowman@amd.com>
References: <20230523232214.55282-1-terry.bowman@amd.com>
        <20230523232214.55282-13-terry.bowman@amd.com>
Organization: Huawei Technologies Research and Development (UK) Ltd.
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On Tue, 23 May 2023 18:22:03 -0500
Terry Bowman <terry.bowman@amd.com> wrote:

> From: Robert Richter <rrichter@amd.com>
> 
> Same as for ports and dports, also store the endpoint's Component
> Register mappings, use struct cxl_dev_state for that.
> 
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/cxlmem.h | 3 ++-
>  drivers/cxl/pci.c    | 9 +++++----
>  2 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index a2845a7a69d8..2823c5aaf3db 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -263,6 +263,7 @@ struct cxl_poison_state {
>   *
>   * @dev: The device associated with this CXL state
>   * @cxlmd: The device representing the CXL.mem capabilities of @dev
> + * @comp_map: component register capability mappings
>   * @regs: Parsed register blocks
>   * @cxl_dvsec: Offset to the PCIe device DVSEC
>   * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
> @@ -299,7 +300,7 @@ struct cxl_poison_state {
>  struct cxl_dev_state {
>  	struct device *dev;
>  	struct cxl_memdev *cxlmd;
> -
> +	struct cxl_register_map comp_map;
>  	struct cxl_regs regs;
>  	int cxl_dvsec;
>  
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 54c486cd65dd..00983770ea7b 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -662,15 +662,16 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>  	 * still be useful for management functions so don't return an error.
>  	 */
>  	cxlds->component_reg_phys = CXL_RESOURCE_NONE;
> -	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> +	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
> +				&cxlds->comp_map);
>  	if (rc)
>  		dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
> -	else if (!map.component_map.ras.valid)
> +	else if (!cxlds->comp_map.component_map.ras.valid)
>  		dev_dbg(&pdev->dev, "RAS registers not found\n");
>  
> -	cxlds->component_reg_phys = map.resource;
> +	cxlds->component_reg_phys = cxlds->comp_map.resource;
>  
> -	rc = cxl_map_component_regs(&map, &cxlds->regs.component,
> +	rc = cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component,
>  				    BIT(CXL_CM_CAP_CAP_ID_RAS));
>  	if (rc)
>  		dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");