Received: by 2002:a05:6358:3188:b0:123:57c1:9b43 with SMTP id q8csp1835331rwd; Fri, 2 Jun 2023 00:21:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7omHCe1JuVBtnWZbDXquNuTtyUsfjxnut7L8vopHV3OVFk8Oj8FKD8q1U2yKHecfm76TYo X-Received: by 2002:a17:90a:185:b0:256:ae6c:fd1f with SMTP id 5-20020a17090a018500b00256ae6cfd1fmr1465638pjc.20.1685690508017; Fri, 02 Jun 2023 00:21:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685690508; cv=none; d=google.com; s=arc-20160816; b=n5vih1KpQrpHRd6Kr0cz914UqVgh3MtsubS4QGUoVnMilS1ld1ghmVDzjg22n4dqbd guNQCB8MfKWq1agV3r3SenxcPcn3jjQCBiaNFKPlR1r0G6CXk0pJttNmFmAu9uMEt15G RI8/FXM9l1a41qy1UOzjTPOHikiWuLzPLMAZ64H0xhUmCsc/Hl5MiNGH1w8SJSawGGqV B29tKUeLzJ7K7zN+7Ga8lfln6kg035pIhPpufwRnhs5Rn92nDeiFyizL2r2i7rK4MoKt jqY2SqKMRJQAzAqM/TzZ48e4vEaftWhKLmEstZvxDsXoVpdFzqoLGFSQqOsceUXhKssO Ny9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=alINskOzJc0qPazeKdcIJuLkY1/n0+xpmOp7jIsdxjQ=; b=Mplai+XNIbEiS73yIP0RgBmNqtazOHz3u+QgoIDqbgGwgxdc2Y5SkpvWUScs3D0CiO AXxK0PS6gHdP5KQSqvTt9w4MWXygnAxS8vtEzqDQ5mntxNUntwYricm0/6KtRuIn/bGw MsTG+Uu4ZAJp914V/1ycrM4WeKexyHYc1A1X3oeCLC8CtL3E9JxZSa3/GxwmdXMDCq0g DuXpFREHDqQt5uKNn0EPj2T/3XjkDhCiU56iveTwRQg3+DkSCcNdCbgkJkCE+eHDEZ7/ MsMKI1hOJc4oL8VwAG7mZ59T9+qS5+uvzNWqH8Ch8DJ1xgbuCKjO0sg/2F0xEdSphLcM Lm4w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g4-20020a17090a300400b0024e35ef410fsi591831pjb.131.2023.06.02.00.21.34; Fri, 02 Jun 2023 00:21:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233907AbjFBHH6 (ORCPT + 99 others); Fri, 2 Jun 2023 03:07:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233879AbjFBHHz (ORCPT ); Fri, 2 Jun 2023 03:07:55 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A223C1AD; Fri, 2 Jun 2023 00:07:30 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 1D9FA8111; Fri, 2 Jun 2023 07:07:26 +0000 (UTC) Date: Fri, 2 Jun 2023 10:07:24 +0300 From: Tony Lindgren To: Nishanth Menon Cc: Conor Dooley , Krzysztof Kozlowski , Rob Herring , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tero Kristo , Vignesh Raghavendra , Udit Kumar , Nitin Yadav , Neha Malcom Francis Subject: Re: [PATCH 1/6] arm64: dts: ti: k3-j721e: Add general purpose timers Message-ID: <20230602070724.GH14287@atomide.com> References: <20230531213215.602395-1-nm@ti.com> <20230531213215.602395-2-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230531213215.602395-2-nm@ti.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Nishanth Menon [230531 21:32]: > There are 20 general purpose timers on j721e that can be used for > things like PWM using pwm-omap-dmtimer driver. There are also > additional ten timers in the MCU domain which are meant for MCU > firmware usage and hence marked reserved by default. > > The odd numbered timers have the option of being cascaded to even > timers to create a 64 bit non-atomic counter which is racy in simple > usage, hence the clock muxes are explicitly setup to individual 32 bit > counters driven off system crystal (HFOSC) as default. > > These instantiation differs from J7200 and other SoCs with the device > IDs and clocks involved for muxing. Reviewed-by: Tony Lindgren