Received: by 2002:a05:6358:3188:b0:123:57c1:9b43 with SMTP id q8csp1915761rwd; Fri, 2 Jun 2023 01:55:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4BdGELGvITnJBzxssdnzGcDHmFUstCR2gB3dMyc1I0QJbh8ChvHTvJcEuH1hcdxydUkS+I X-Received: by 2002:a0d:e24d:0:b0:561:949d:a7fd with SMTP id l74-20020a0de24d000000b00561949da7fdmr12227649ywe.45.1685696141954; Fri, 02 Jun 2023 01:55:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685696141; cv=none; d=google.com; s=arc-20160816; b=JnDPhWX5LzR9ZJz0T+/VtJYNTLBYKiACUc52I6nST2iF2Zeb/SzIHGRLDkS9IWiE1E jK0pgeEFnP2NluE+sKgZD5dG/4qDpJ9fFr6UhxRxA90I4GovQFuMdOlXpZ7fQrtK4R2u DbSsQDK6jdtup8BascwS+yixySks0HFdn3+mboPysO8etB6J0d4+MnPT/C5wf6ZYJDXu HwNmA9HiA7kbGJUqn6AONRH/149aKA6WuwCHbdWriLLdZe6hp8jZOfr2FreR10X7mNWW nV+mo5/xlWHgjoU9BaN7P9O1gbwBPCroHFfD02bnyRMjZg/KVQuiGbo0XRtGS5MyMRDo RB0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=BoBbkS/zUIFXaUMoK3coeCqBjfs5OoUOuWlPLNqaHq8=; b=OSamfKCkufGfC06kmm+wAdOCxgOhvW0KFx275So/5VCXCJeVwHfghv1xPJKjl+jwuX R7uKfkZUWkTcll0QGlJntMLsZ5uTX3yNEOe2Mmqpy1m85k67raVWgv26CMcFENno0DRM BEah7ba0Z/3hIx/Z43dWm2URA2sZ8xYAwqzHpDscaxQ2wHSwCoR5UBxghBnxbKLuec0f Uw3qWJUI6P98dNUKHXAzDB78MfPJqCSLucShfC5+kMGlgfMUcSyBjE90gDpV80VhtqNC bCdQYA05SaP0cp823sKG7aatOiNH/NQBV/GziWkG+MvKXTMR0kNTo/4g8by4tQjvgygK LyMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 145-20020a621997000000b0064f32a066b7si391097pfz.251.2023.06.02.01.55.27; Fri, 02 Jun 2023 01:55:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234760AbjFBIuA convert rfc822-to-8bit (ORCPT + 99 others); Fri, 2 Jun 2023 04:50:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234121AbjFBIte (ORCPT ); Fri, 2 Jun 2023 04:49:34 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4131E51; Fri, 2 Jun 2023 01:49:31 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 1F96424E276; Fri, 2 Jun 2023 16:49:29 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 2 Jun 2023 16:49:29 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 2 Jun 2023 16:49:28 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Date: Fri, 2 Jun 2023 16:49:24 +0800 Message-ID: <20230602084925.215411-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602084925.215411-1-william.qiu@starfivetech.com> References: <20230602084925.215411-1-william.qiu@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add QSPI clock operation in device probe. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 6ddb2dfc0f00..21788472c7fb 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -63,6 +63,8 @@ struct cqspi_st { struct platform_device *pdev; struct spi_master *master; struct clk *clk; + struct clk_bulk_data *clks; + unsigned int num_clks; unsigned int sclk; void __iomem *iobase; @@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev) } if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); + if (cqspi->num_clks < 0) { + dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks); + return -EINVAL; + } + + ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); + if (ret) + dev_err(dev, "Cannot enable clock clks\n"); + rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret = PTR_ERR(rstc_ref); @@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } @@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + return ret; } @@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); clk_prepare_enable(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); cqspi_wait_idle(cqspi); cqspi_controller_init(cqspi); -- 2.34.1