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Date:   Fri, 2 Jun 2023 16:16:01 +0200
From:   Robert Richter <rrichter@amd.com>
To:     Jonathan Cameron <Jonathan.Cameron@huawei.com>
CC:     Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
        <vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
        <bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
        <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
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Subject: Re: [PATCH v4 01/23] cxl/acpi: Probe RCRB later during RCH
 downstream port creation
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Hi Jonathan,

On 01.06.23 11:13:28, Jonathan Cameron wrote:
> On Tue, 23 May 2023 18:21:52 -0500
> Terry Bowman <terry.bowman@amd.com> wrote:
> 
> > From: Robert Richter <rrichter@amd.com>
> > 
> > The RCRB is extracted already during ACPI CEDT table parsing while the
> > data of this is needed not earlier than dport creation. This
> > implementation comes with drawbacks: During ACPI table scan there is
> > already MMIO access including mapping and unmapping, but only ACPI
> > data should be collected here. The collected data must be transferred
> > through a couple of interfaces until it is finally consumed when
> > creating the dport. This causes complex data structures and function
> > interfaces. Additionally, RCRB parsing will be extended to also
> > extract AER data, it would be much easier do this at a later point
> > during port and dport creation when the data structures are available
> > to hold that data.
> > 
> > To simplify all that, probe the RCRB at a later point during RCH
> > downstream port creation. Change ACPI table parser to only extract the
> > base address of either the component registers or the RCRB. Parse and
> > extract the RCRB in devm_cxl_add_rch_dport().
> > 
> > This is in preparation to centralize all RCRB scanning.
> > 
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> 
> Hi,
> 
> Some comments inline, though one of them (about extensibility of CDAT
> structures) applies just as much to the existing code so doesn't affect
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> for this patch.

thanks for review. See inline.

> 
> 
> > ---
> >  drivers/cxl/acpi.c      | 52 ++++++++++++++++-------------------------
> >  drivers/cxl/core/port.c | 21 +++++++++++++----
> >  drivers/cxl/cxl.h       |  1 -
> >  3 files changed, 36 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> > index 7e1765b09e04..39227070da9b 100644
> > --- a/drivers/cxl/acpi.c
> > +++ b/drivers/cxl/acpi.c
> > @@ -373,20 +373,18 @@ static int add_host_bridge_uport(struct device *match, void *arg)
> >  }
> >  
> >  struct cxl_chbs_context {
> > -	struct device *dev;
> >  	unsigned long long uid;
> > -	resource_size_t rcrb;
> > -	resource_size_t chbcr;
> > +	resource_size_t base;
> >  	u32 cxl_version;
> >  };
> >  
> > -static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
> > +static int cxl_get_chbs(union acpi_subtable_headers *header, void *arg,
> >  			 const unsigned long end)
> >  {
> >  	struct cxl_chbs_context *ctx = arg;
> >  	struct acpi_cedt_chbs *chbs;
> >  
> > -	if (ctx->chbcr)
> > +	if (ctx->base)
> >  		return 0;
> >  
> >  	chbs = (struct acpi_cedt_chbs *) header;
> > @@ -395,23 +393,16 @@ static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
> >  		return 0;
> >  
> >  	ctx->cxl_version = chbs->cxl_version;
> > -	ctx->rcrb = CXL_RESOURCE_NONE;
> > -	ctx->chbcr = CXL_RESOURCE_NONE;
> > +	ctx->base = CXL_RESOURCE_NONE;
> >  
> >  	if (!chbs->base)
> >  		return 0;
> >  
> > -	if (chbs->cxl_version != ACPI_CEDT_CHBS_VERSION_CXL11) {
> > -		ctx->chbcr = chbs->base;
> 
> Trivial: This is a functional change and should be called out -
> previously the base address was stashed even if the length test
> fails, now it isn't. May make no difference because it was never used
> if that's the case, but would be nice to still mention it in patch description.

The logic changed but the intention is to have the same checks as
before. The length check is in only for the CXL11 case and no check
for VH mode. This is implemented as before and no functional change,
note the check later below in the old code which was the CXL11-only
path.

> 
> Also, ACPI tables are designed to be extensible and I think that
> applies to CDAT tables as well - so this code should not be
> checking for a precise match, but rather that it is greater than
> or equal to the size we will read from.

I don't think the spec will change here as this is limited to RCD mode
only. Other than e.g. capability register ranges this is a block size,
there is no intention to extend it.

> 
> 
> > +	if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11 &&
> > +	    chbs->length != CXL_RCRB_SIZE)
> >  		return 0;
> > -	}
> 
> >  
> > -	if (chbs->length != CXL_RCRB_SIZE)
> > -		return 0;

Note this check here.

-Robert

> > -
> > -	ctx->rcrb = chbs->base;
> > -	ctx->chbcr = cxl_rcrb_to_component(ctx->dev, chbs->base,
> > -					   CXL_RCRB_DOWNSTREAM);
> > +	ctx->base = chbs->base;
> >  
> >  	return 0;
> >  }
>