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Date:   Fri, 2 Jun 2023 17:43:25 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Torsten Duwe <duwe@lst.de>
Cc:     Xingyu Wu <xingyu.wu@starfivetech.com>,
        Conor Dooley <conor.dooley@microchip.com>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        yanhong.wang@starfivetech.com,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        William Qiu <william.qiu@starfivetech.com>,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock
 generator
Message-ID: <20230602-drained-wheat-b6c5ea009f16@spud>
References: <20230512022036.97987-1-xingyu.wu@starfivetech.com>
 <20230512022036.97987-2-xingyu.wu@starfivetech.com>
 <20230519135733.GA10188@lst.de>
 <20230519-smokeless-guileless-2a71cae06509@wendy>
 <df43411e-8982-74f5-6148-e7281c37dada@starfivetech.com>
 <20230602183922.649b8e88@blackhole.lan>
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On Fri, Jun 02, 2023 at 06:39:22PM +0200, Torsten Duwe wrote:
> On Tue, 23 May 2023 10:56:43 +0800
> Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>=20
> > On 2023/5/19 22:16, Conor Dooley wrote:
> > > On Fri, May 19, 2023 at 03:57:33PM +0200, Torsten Duwe wrote:
> > >> On Fri, May 12, 2023 at 10:20:30AM +0800, Xingyu Wu wrote:
> > >> [...]
> > >> >  #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
> > >> >  #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
> > >> > =20
> > >> > +/* PLL clocks */
> > >> > +#define JH7110_CLK_PLL0_OUT			0
> > >> > +#define JH7110_CLK_PLL1_OUT			1
> > >> > +#define JH7110_CLK_PLL2_OUT			2
> > >>=20
> > >> In U-Boot commit 58c9c60b Yanhong Wang added:
> > >>=20
> > >> +
> > >> +#define JH7110_SYSCLK_PLL0_OUT                       190
> > >> +#define JH7110_SYSCLK_PLL1_OUT                       191
> > >> +#define JH7110_SYSCLK_PLL2_OUT                       192
> > >> +
> > >> +#define JH7110_SYSCLK_END                    193
> > >>=20
> > >> in that respective file.
> > >>=20
> > >> > +#define JH7110_PLLCLK_END			3
> > >> > +
> > >> >  /* SYSCRG clocks */
> > >> >  #define JH7110_SYSCLK_CPU_ROOT			0
> > >>=20
> > >> If the symbolic names referred to the same items, would it be possib=
le
> > >> to keep the two files in sync somehow?
> > >=20
> > > Ohh, that's not good.. If you pass the U-Boot dtb to Linux it won't
> > > understand the numbering. The headers are part of the dt-binding :/
> >=20
> > Because PLL driver is separated from SYSCRG drivers in Linux,
>=20
> Can you _please_ point me at that "PLL driver" "in Linux" ?

It's patch 2 in this series:
https://lore.kernel.org/linux-riscv/20230512022036.97987-1-xingyu.wu@starfi=
vetech.com/T/#m4b2d74c36b3bb961a1187ec5cda1a0a0de875f0e

HTH,
Conor.

> I seem to be unable to find it. All I can see is a stub in
> drivers/clk/starfive/clk-starfive-jh7110-sys.c, which simply
> sets the PLLs to 1000, 1066 and 1188 MHz fixed, respectively.
>=20
> The comment above says
>=20
> | They will be dropped and registered in the PLL clock driver instead.
>=20
> and that's the one I'm looking for.
>=20
> Thanks,
>=20
> 	Torsten

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