Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Received-SPF: Pass (protection.outlook.com: domain of amd.com designates
 165.204.84.17 as permitted sender) receiver=protection.outlook.com;
 client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C
Date:   Fri, 2 Jun 2023 18:41:57 +0200
From:   Robert Richter <rrichter@amd.com>
To:     Jonathan Cameron <Jonathan.Cameron@huawei.com>
CC:     Bjorn Helgaas <helgaas@kernel.org>,
        Terry Bowman <terry.bowman@amd.com>,
        <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
        <ira.weiny@intel.com>, <bwidawsk@kernel.org>,
        <dan.j.williams@intel.com>, <dave.jiang@intel.com>,
        <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <bhelgaas@google.com>
Subject: Re: [PATCH v4 23/23] PCI/AER: Unmask RCEC internal errors to enable
 RCH downstream port error handling
Message-ID: <ZHob1YA3NUFNushM@rric.localdomain>
References: <ZG/cYUaZerXNqqJl@rric.localdomain>
 <ZHEXOlxfCCApI+NE@bhelgaas>
 <20230601151134.00006281@Huawei.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20230601151134.00006281@Huawei.com>
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2023 16:42:03.4132
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: ad1784c3-60c5-4596-4450-08db63884b72
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com]
X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT112.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6814
X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,
        RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,
        T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no
        version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 01.06.23 15:11:34, Jonathan Cameron wrote:
> 
> > > > > @@ -1432,6 +1495,7 @@ static int aer_probe(struct pcie_device *dev)
> > > > >  		return status;
> > > > >  	}
> > > > >  
> > > > > +	cxl_rch_enable_rcec(port);  
> > > > 
> > > > Could this be done by the driver that claims the CXL RCiEP?  There's
> > > > no point in unmasking the errors before there's a driver with
> > > > pci_error_handlers that can do something with them anyway.  
> > > 
> > > This sounds reasonable at the first glance. The problem is there could
> > > be many devices associated with the RCEC. Not all of them will be
> > > bound to a driver and handler at the same time. We would need to
> > > refcount it or maintain a list of enabled devices. But there is
> > > already something similar by checking dev->driver. But right, AER
> > > errors could be seen and handled then at least on PCI level. I tent to
> > > permanently enable RCEC AER, but that could cause side-effects. What
> > > do you think?  
> > 
> > IIUC, this really just affects CXL devices, so I think the choice is
> > (1) always unmask internal errors for RCECs where those CXL devices
> > report errors (as this patch does), or (2) unmask when first CXL
> > driver that can handle the errors is loaded and restore previous state
> > when last one is unloaded.
> > 
> > If the RCEC *only* handles errors for CXL devices, i.e., not for a mix
> > of vanilla PCIe RCiEPs and CXL RCiEPs, I think I'm OK with (1).  I
> > think you said only the CXL driver knows how to collect and interpret
> > the error data.  Is it OK that when no such driver is loaded, we field
> > error interrupts silently, without even mentioning that an error
> > occurred?  I guess without the driver, the device is probably not in
> > use.
> 
> It might be in use.  Firmware may well have set up the CXL device and
> even have put the kernel image in that memory for example. OS first RAS
> handling won't be up until the driver loads though.  Would be a bit
> odd to mix OS first handling with firmware setup. I'd expect firmware
> first handling in that case, but I don't think anything stops the two
> being mixed.

Right, CXL memory may have been set up by firmware. We will only see
AER errors (for the unmasked error types) then without further CXL
handling, which is IMO OK.

This all assumes a non-CXL aware system can clear the error status by
only using PCIe AER. That is, a CXL RAS error may not trigger again
(or at all) by only clearing the AER status and not the CXL RAS status
in the capability. I don't know what the spec says here and how
devices actually operate.

Maybe option (2) is easy to implement with the refcount_t API. So with
the first device probed we just enable the RCEC's internal errors and
disable them when the last device is removed. I think CXL RAS errors
will not be triggered then as internal error must be enabled for this,
either in the RCEC or the endpoint. Since internal errors must be
unmasked first which can only be done by the CXL driver, CXL RAS error
wont trigger an AER error message.

Thanks,

-Robert