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References: <20230601214814.2329224-1-olvaffe@gmail.com>
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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Fri, 2 Jun 2023 14:19:43 -0400
Message-ID: <CADnq5_NQ2zgvRDZ8NWUsCm-8JO6PZSEmQ+WrbjYqjv3vTLfinw@mail.gmail.com>
Subject: Re: [PATCH] drm/amdgpu: fix xclk freq on CHIP_STONEY
To:     Chia-I Wu <olvaffe@gmail.com>
Cc:     dri-devel@lists.freedesktop.org,
        "Pan, Xinhui" <Xinhui.Pan@amd.com>, linux-kernel@vger.kernel.org,
        amd-gfx@lists.freedesktop.org, Le Ma <le.ma@amd.com>,
        Kai-Heng Feng <kai.heng.feng@canonical.com>,
        Mario Limonciello <mario.limonciello@amd.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Alex Deucher <alexander.deucher@amd.com>,
        Likun Gao <Likun.Gao@amd.com>,
        David Airlie <airlied@gmail.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>,
        Hawking Zhang <Hawking.Zhang@amd.com>
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Applied.  Thanks!

Alex

On Thu, Jun 1, 2023 at 5:48=E2=80=AFPM Chia-I Wu <olvaffe@gmail.com> wrote:
>
> According to Alex, most APUs from that time seem to have the same issue
> (vbios says 48Mhz, actual is 100Mhz).  I only have a CHIP_STONEY so I
> limit the fixup to CHIP_STONEY
> ---
>  drivers/gpu/drm/amd/amdgpu/vi.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu=
/vi.c
> index 770f2d7a371fc..6a8494f98d3ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -542,8 +542,15 @@ static u32 vi_get_xclk(struct amdgpu_device *adev)
>         u32 reference_clock =3D adev->clock.spll.reference_freq;
>         u32 tmp;
>
> -       if (adev->flags & AMD_IS_APU)
> -               return reference_clock;
> +       if (adev->flags & AMD_IS_APU) {
> +               switch (adev->asic_type) {
> +               case CHIP_STONEY:
> +                       /* vbios says 48Mhz, but the actual freq is 100Mh=
z */
> +                       return 10000;
> +               default:
> +                       return reference_clock;
> +               }
> +       }
>
>         tmp =3D RREG32_SMC(ixCG_CLKPIN_CNTL_2);
>         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
> --
> 2.41.0.rc0.172.g3f132b7071-goog
>