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Message-ID: <e928c95e-dbce-d298-8c53-b54d0f796643@quicinc.com>
Date:   Sat, 3 Jun 2023 13:21:48 +0530
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Subject: Re: [PATCH 2/2] arm64: dts: qcom: ipq9574: add support for RDP453
 variant
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To:     Konrad Dybcio <konrad.dybcio@linaro.org>, <agross@kernel.org>,
        <andersson@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
CC:     <quic_srichara@quicinc.com>, <quic_sjaganat@quicinc.com>,
        <quic_kathirav@quicinc.com>, <quic_arajkuma@quicinc.com>,
        <quic_anusha@quicinc.com>
References: <20230526153152.777-1-quic_devipriy@quicinc.com>
 <20230526153152.777-3-quic_devipriy@quicinc.com>
 <61e81ac1-d7e2-a909-2e39-dad315acf8fe@linaro.org>
From:   Devi Priya <quic_devipriy@quicinc.com>
In-Reply-To: <61e81ac1-d7e2-a909-2e39-dad315acf8fe@linaro.org>
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On 5/27/2023 2:15 AM, Konrad Dybcio wrote:
> 
> 
> On 26.05.2023 17:31, Devi Priya wrote:
>> Add the initial device tree support for the Reference Design Platform (RDP)
>> 453 based on IPQ9574 family of SoCs. This patch adds support for Console
>> UART, SPI NOR and SMPA1 regulator node.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> 
> BTW what's the naming scheme for IPQ?
> 
> IPQabcd
> 
> 'a' - tier
> 'b' - 0/5 - network generation dependent?
> 'cd' - model
> 
> ?
> 
Hi konrad,

Below is the naming scheme,
IPQabcd
a-> product category(5-Immersive home, 6-Home, 9-Networking Pro)
b-> generation (5-Alder)
c-> SKU customization (0-base SKU)
d-> #chains

Thanks,
Devi Priya
> Konrad
>>   arch/arm64/boot/dts/qcom/Makefile           |  1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 80 +++++++++++++++++++++
>>   2 files changed, 81 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 834e790bec90..56ec3d84ad43 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp418.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp433.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp449.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp453.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-rdp454.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-acer-a1-724.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
>> new file mode 100644
>> index 000000000000..f01de6628c3b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
>> @@ -0,0 +1,80 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * IPQ9574 RDP453 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";
>> +	compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&blsp1_spi0 {
>> +	pinctrl-0 = <&spi_0_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +
>> +	flash@0 {
>> +		compatible = "micron,n25q128a11", "jedec,spi-nor";
>> +		reg = <0>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		spi-max-frequency = <50000000>;
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	pinctrl-0 = <&uart2_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&rpm_requests {
>> +	regulators {
>> +		compatible = "qcom,rpm-mp5496-regulators";
>> +
>> +		ipq9574_s1: s1 {
>> +		/*
>> +		 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> +		 * During regulator registration, kernel not knowing the initial voltage,
>> +		 * considers it as zero and brings up the regulators with minimum supported voltage.
>> +		 * Update the regulator-min-microvolt with SVS voltage of 725mV so that
>> +		 * the regulators are brought up with 725mV which is sufficient for all the
>> +		 * corner parts to operate at 800MHz
>> +		 */
>> +			regulator-min-microvolt = <725000>;
>> +			regulator-max-microvolt = <1075000>;
>> +		};
>> +	};
>> +};
>> +
>> +&sleep_clk {
>> +	clock-frequency = <32000>;
>> +};
>> +
>> +&tlmm {
>> +	spi_0_pins: spi-0-state {
>> +		pins = "gpio11", "gpio12", "gpio13", "gpio14";
>> +		function = "blsp0_spi";
>> +		drive-strength = <8>;
>> +		bias-disable;
>> +	};
>> +};
>> +
>> +&xo_board_clk {
>> +	clock-frequency = <24000000>;
>> +};