Received: by 2002:a05:6358:3188:b0:123:57c1:9b43 with SMTP id q8csp5161612rwd; Sun, 4 Jun 2023 22:20:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7mEblhloWzodUGE6PjwUDjuyy+3nVKVFVgOacr7c4XzGMTTrVUhrgFQZOF4R/hkAorOBBH X-Received: by 2002:a05:6214:528f:b0:628:3e37:e14f with SMTP id kj15-20020a056214528f00b006283e37e14fmr6306823qvb.33.1685942406466; Sun, 04 Jun 2023 22:20:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685942406; cv=none; d=google.com; s=arc-20160816; b=RFedRA1JGdprShb870lN5kid01kiunL1gwbwRT0vM/oVrD0Zhc6X9anxRzIXyi68iB XaMXAF6rQaKzB1z1ElVVrH7hgMHsZYiBig2pMTdRcQy/hzWgMMCnFJRH+CrAdu54mBxe JlVp5yFH7h8oxc14dMS5XCpkw7IBRpWcWTXEcT9Xh0qlFr2ZGW6TKZ91RnTpXR1N6LF4 zXHhXWzcpKVJKNeV7lLTAPsRkoTsl+pSlZMYvaQ/DUG1gHT+d67EGJsfciHpXjSvslXO KFCM5Biu7ksmMJBUvP1CV5cqRTC94DIlterJzDzzJ10d46tVX5WfR0PQvoneZ1X5fVuH coDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=xuO9eLcYnZTW8XryeXClAmX0YvIXweJqzplHXpKbjPE=; b=J6IsI9XjXRkt4SXA3ascX3GmxkWXEenRryrLhLCtKvifESObm5H58EyfYtztbiMayX ZrTieH2jnxl/3BtP1SPwkvOnhBIsba4Asi5JoTk1hO9IE36jYZhN+irQl5XWO2qTeHLZ D90TwGMQ10cdW3bcU7PIt2IUyNfzcDSZn73Tkud33Ub6Z6yL0I9dxq6SfqFooxtTrZYs HdP3IkR6+OcslWKVoexcX2dZHQomQ+2cQPQC5C9Yn4EyoUhPKYoRXmRqmxmayNs3dV0Q Jz4aVlJRCoG7p7Jv/WSN6WOoGugBLa+RGMIZFQJrvHK9+j+ND5BunyVimm1KoNHlO2XM oSbg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e14-20020a17090301ce00b001b0044f186fsi5043618plh.41.2023.06.04.22.19.51; Sun, 04 Jun 2023 22:20:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232180AbjFEEyc (ORCPT + 99 others); Mon, 5 Jun 2023 00:54:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231280AbjFEEya (ORCPT ); Mon, 5 Jun 2023 00:54:30 -0400 Received: from muru.com (muru.com [72.249.23.125]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2BEBEB1; Sun, 4 Jun 2023 21:54:29 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 5CED280C1; Mon, 5 Jun 2023 04:54:28 +0000 (UTC) Date: Mon, 5 Jun 2023 07:54:27 +0300 From: Tony Lindgren To: Udit Kumar Cc: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, conor+dt@kernel.org, m-chawdhry@ti.com, n-francis@ti.com Subject: Re: [PATCH v3 1/5] arm64: dts: ti: k3-j7200: Add general purpose timers Message-ID: <20230605045427.GV14287@atomide.com> References: <20230604045525.1889083-1-u-kumar1@ti.com> <20230604045525.1889083-2-u-kumar1@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230604045525.1889083-2-u-kumar1@ti.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Udit Kumar [230604 04:57]: > There are 20 general purpose timers on j721e that can be used for > things like PWM using pwm-omap-dmtimer driver. There are also > additional ten timers in the MCU domain which are meant for MCU > firmware usage and hence marked reserved by default. > > The odd numbered timers have the option of being cascaded to even > timers to create a 64 bit non-atomic counter which is racy in simple > usage, hence the clock muxes are explicitly setup to individual 32 bit > counters driven off system crystal (HFOSC) as default. Reviewed-by: Tony Lindgren