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From:   Thomas Gleixner <tglx@linutronix.de>
To:     Xin Li <xin3.li@intel.com>, linux-kernel@vger.kernel.org,
        x86@kernel.org, kvm@vger.kernel.org
Cc:     mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
        hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com,
        seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com,
        jiangshanlai@gmail.com, shan.kang@intel.com
Subject: Re: [PATCH v8 09/33] x86/cpu: add X86_CR4_FRED macro
In-Reply-To: <20230410081438.1750-10-xin3.li@intel.com>
References: <20230410081438.1750-1-xin3.li@intel.com>
 <20230410081438.1750-10-xin3.li@intel.com>
Date:   Mon, 05 Jun 2023 14:01:41 +0200
Message-ID: <87r0qq6rtm.ffs@tglx>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk

On Mon, Apr 10 2023 at 01:14, Xin Li wrote:

> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
>
> Add X86_CR4_FRED macro for the FRED bit in %cr4. This bit should be a

s/should/must/ no?

> +/*
> + * These bits should not change their value after CPU init is finished.
> + * The explicit cast to unsigned long suppresses a warning on i386 for
> + * x86-64 only feature bits >= 32.
> + */
>  static const unsigned long cr4_pinned_mask =
> -	X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
> -	X86_CR4_FSGSBASE | X86_CR4_CET;
> +	(unsigned long)

That type cast is required because:

+#define X86_CR4_FRED		_BITULL(X86_CR4_FRED_BIT)

Bah. Fred is 64 bit only. So why defining this as 1ULL << 32
unconditionally and stripping the bit off on 32bit via the type cast?

#ifdef CONFIG_X86_64
#define X86_CR4_FRED		_BITUL(X86_CR4_FRED_BIT)
#else
#define X86_CR4_FRED		0
#endif

would be too obvious, right?

> +	(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
> +	 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED);

Thanks,

        tglx