Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <e420c3dd-033b-b0db-ecfa-7165b9990270@ti.com>
Date:   Mon, 5 Jun 2023 17:40:16 +0530
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
 Thunderbird/102.11.0
Subject: Re: [PATCH] arm64: dts: ti: k3-j721s2: Change CPTS clock parent
Content-Language: en-US
To:     Nishanth Menon <nm@ti.com>
CC:     <linux-arm-kernel@lists.infradead.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <vigneshr@ti.com>, <kristo@kernel.org>
References: <20230605110443.84568-1-n-francis@ti.com>
 <20230605114924.56ccpd6rvddnr463@undying>
From:   Neha Malcom Francis <n-francis@ti.com>
In-Reply-To: <20230605114924.56ccpd6rvddnr463@undying>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 7bit
Precedence: bulk

Hi Nishanth

On 05/06/23 17:19, Nishanth Menon wrote:
> On 16:34-20230605, Neha Malcom Francis wrote:
>> MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's
>> capability to re-initialise clock frequencies. CPTS and RGMII has
>> MAIN_PLL3 as their parent which does not have this flag. While RGMII
>> needs this reinitialisation to default frequency to be able to get
>> 250MHz with its divider, CPTS can not get its required 200MHz with its
>> divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
>> MAIN_PLL0_HSDIV6.
>>
>> (Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side
>> for the same reason)
>>
>> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi       | 2 ++
>>   arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++
> 
> 
> Is this the only device with this change? or are we doing that across
> the board? if so, could you please do this in a single series so that we
> don't have a mix?
> 

Currently, this is the only device that has moved this flag in DM side. 
None of the other devices (except for J784S4 which also made a similar 
change both in DM and U-BOOT) have this change in flag for the upcoming 
firmware release.

>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> index 2dd7865f7654..331e0c9b4db8 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>> @@ -738,6 +738,8 @@ cpts@310d0000 {
>>   			reg-names = "cpts";
>>   			clocks = <&k3_clks 226 5>;
>>   			clock-names = "cpts";
>> +			assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
>> +			assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
>>   			interrupts-extended = <&main_navss_intr 391>;
>>   			interrupt-names = "cpts";
>>   			ti,cpts-periodic-outputs = <6>;
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
>> index a353705a7463..b55a3e9daf85 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
>> @@ -333,6 +333,8 @@ cpts@3d000 {
>>   			reg = <0x0 0x3d000 0x0 0x400>;
>>   			clocks = <&k3_clks 29 3>;
>>   			clock-names = "cpts";
>> +			assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
>> +			assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
>>   			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
>>   			interrupt-names = "cpts";
>>   			ti,cpts-ext-ts-inputs = <4>;
>> -- 
>> 2.34.1
>>
> 

-- 
Thanking You
Neha Malcom Francis