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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x19-20020a656ab3000000b00530b7ce3d34si5654564pgu.305.2023.06.05.08.09.09; Mon, 05 Jun 2023 08:09:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=s8WeajpR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233729AbjFEOzF (ORCPT + 99 others); Mon, 5 Jun 2023 10:55:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231848AbjFEOzD (ORCPT ); Mon, 5 Jun 2023 10:55:03 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3ADCFA7; Mon, 5 Jun 2023 07:55:01 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 355Esj51062222; Mon, 5 Jun 2023 09:54:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685976885; bh=vxMCzKRwtzY1Fxt2/u4RPjPGdC3o6YbydC6naG5DWBQ=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=s8WeajpRiz2/fe1ZXaVzgR7vctDCJ6Xf6k4TkIfc2Kl2OIbhRSd2+pI1ZaP+49eNX Ndkt/MDXHmjSUsZvnwJnB6Mc193HusOx4mZ5uVHkdYngCHmgAXj/9z/f+K/mQnFrSS zD5yoczkOUW3/O4gF9nxHwPmbhZ4Xr0smv39aFtQ= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 355Esji9008784 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 5 Jun 2023 09:54:45 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 5 Jun 2023 09:54:45 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 5 Jun 2023 09:54:45 -0500 Received: from [10.250.212.205] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 355EsfFP026904; Mon, 5 Jun 2023 09:54:42 -0500 Message-ID: Date: Mon, 5 Jun 2023 20:24:40 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 2/5] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes Content-Language: en-US To: Andrew Davis , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Robert Nelson CC: , , , achal Verma References: <20230515172137.474626-1-afd@ti.com> <20230515172137.474626-2-afd@ti.com> <1de1328a-cfc9-d77c-eb11-3c341b46623b@ti.com> <4ff112d9-5c94-e7eb-8c94-4be769285a03@ti.com> From: "Verma, Achal" In-Reply-To: <4ff112d9-5c94-e7eb-8c94-4be769285a03@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/16/2023 9:57 PM, Andrew Davis wrote: > On 5/16/23 11:22 AM, Verma, Achal wrote: >> >> >> On 5/15/2023 10:51 PM, Andrew Davis wrote: >>> These nodes are example nodes for the PCIe controller in "endpoint" >>> mode. >>> By default the controller is in "root complex" mode and there is >>> already a >>> DT node for the same. >>> >>> Examples should go in the bindings or other documentation. >>> >>> Remove this node. >> How we will support EP from now onwards, using overlays ? >> > > They are already disabled, how do you support them today? As of now we edit the DTS (disable RC node and enable EP mode) but now we have to delete RC node and add EP node and build DTBS which looks like quite a work. Regards, Achal Verma > > Andrew > >> Regards, >> Achal Verma >>> >>> Signed-off-by: Andrew Davis >>> --- >>>   .../boot/dts/ti/k3-j721e-beagleboneai64.dts   | 24 ------ >>>   .../dts/ti/k3-j721e-common-proc-board.dts     | 25 ------ >>>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 82 ------------------- >>>   arch/arm64/boot/dts/ti/k3-j721e-sk.dts        | 24 ------ >>>   4 files changed, 155 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts >>> b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts >>> index 8a62ac263b89..d77eeff0d81d 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts >>> @@ -892,35 +892,11 @@ &pcie2_rc { >>>       status = "disabled"; >>>   }; >>> -&pcie0_ep { >>> -    status = "disabled"; >>> -    phys = <&serdes0_pcie_link>; >>> -    phy-names = "pcie-phy"; >>> -    num-lanes = <1>; >>> -}; >>> - >>> -&pcie1_ep { >>> -    status = "disabled"; >>> -    phys = <&serdes1_pcie_link>; >>> -    phy-names = "pcie-phy"; >>> -    num-lanes = <2>; >>> -}; >>> - >>> -&pcie2_ep { >>> -    /* Unused */ >>> -    status = "disabled"; >>> -}; >>> - >>>   &pcie3_rc { >>>       /* Unused */ >>>       status = "disabled"; >>>   }; >>> -&pcie3_ep { >>> -    /* Unused */ >>> -    status = "disabled"; >>> -}; >>> - >>>   &icssg0_mdio { >>>       /* Unused */ >>>       status = "disabled"; >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts >>> b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts >>> index 7db0603125aa..87b7263f6547 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts >>> @@ -840,35 +840,10 @@ &pcie2_rc { >>>       num-lanes = <2>; >>>   }; >>> -&pcie0_ep { >>> -    phys = <&serdes0_pcie_link>; >>> -    phy-names = "pcie-phy"; >>> -    num-lanes = <1>; >>> -    status = "disabled"; >>> -}; >>> - >>> -&pcie1_ep { >>> -    phys = <&serdes1_pcie_link>; >>> -    phy-names = "pcie-phy"; >>> -    num-lanes = <2>; >>> -    status = "disabled"; >>> -}; >>> - >>> -&pcie2_ep { >>> -    phys = <&serdes2_pcie_link>; >>> -    phy-names = "pcie-phy"; >>> -    num-lanes = <2>; >>> -    status = "disabled"; >>> -}; >>> - >>>   &pcie3_rc { >>>       status = "disabled"; >>>   }; >>> -&pcie3_ep { >>> -    status = "disabled"; >>> -}; >>> - >>>   &icssg0_mdio { >>>       status = "disabled"; >>>   }; >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> index 10c8a5fb4ee2..e39f6d1e8d40 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >>> @@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 { >>>           dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; >>>       }; >>> -    pcie0_ep: pcie-ep@2900000 { >>> -        compatible = "ti,j721e-pcie-ep"; >>> -        reg = <0x00 0x02900000 0x00 0x1000>, >>> -              <0x00 0x02907000 0x00 0x400>, >>> -              <0x00 0x0d000000 0x00 0x00800000>, >>> -              <0x00 0x10000000 0x00 0x08000000>; >>> -        reg-names = "intd_cfg", "user_cfg", "reg", "mem"; >>> -        interrupt-names = "link_state"; >>> -        interrupts = ; >>> -        ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; >>> -        max-link-speed = <3>; >>> -        num-lanes = <2>; >>> -        power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; >>> -        clocks = <&k3_clks 239 1>; >>> -        clock-names = "fck"; >>> -        max-functions = /bits/ 8 <6>; >>> -        max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; >>> -        dma-coherent; >>> -    }; >>> - >>>       pcie1_rc: pcie@2910000 { >>>           compatible = "ti,j721e-pcie-host"; >>>           reg = <0x00 0x02910000 0x00 0x1000>, >>> @@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 { >>>           dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; >>>       }; >>> -    pcie1_ep: pcie-ep@2910000 { >>> -        compatible = "ti,j721e-pcie-ep"; >>> -        reg = <0x00 0x02910000 0x00 0x1000>, >>> -              <0x00 0x02917000 0x00 0x400>, >>> -              <0x00 0x0d800000 0x00 0x00800000>, >>> -              <0x00 0x18000000 0x00 0x08000000>; >>> -        reg-names = "intd_cfg", "user_cfg", "reg", "mem"; >>> -        interrupt-names = "link_state"; >>> -        interrupts = ; >>> -        ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; >>> -        max-link-speed = <3>; >>> -        num-lanes = <2>; >>> -        power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; >>> -        clocks = <&k3_clks 240 1>; >>> -        clock-names = "fck"; >>> -        max-functions = /bits/ 8 <6>; >>> -        max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; >>> -        dma-coherent; >>> -    }; >>> - >>>       pcie2_rc: pcie@2920000 { >>>           compatible = "ti,j721e-pcie-host"; >>>           reg = <0x00 0x02920000 0x00 0x1000>, >>> @@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 { >>>           dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; >>>       }; >>> -    pcie2_ep: pcie-ep@2920000 { >>> -        compatible = "ti,j721e-pcie-ep"; >>> -        reg = <0x00 0x02920000 0x00 0x1000>, >>> -              <0x00 0x02927000 0x00 0x400>, >>> -              <0x00 0x0e000000 0x00 0x00800000>, >>> -              <0x44 0x00000000 0x00 0x08000000>; >>> -        reg-names = "intd_cfg", "user_cfg", "reg", "mem"; >>> -        interrupt-names = "link_state"; >>> -        interrupts = ; >>> -        ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; >>> -        max-link-speed = <3>; >>> -        num-lanes = <2>; >>> -        power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; >>> -        clocks = <&k3_clks 241 1>; >>> -        clock-names = "fck"; >>> -        max-functions = /bits/ 8 <6>; >>> -        max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; >>> -        dma-coherent; >>> -    }; >>> - >>>       pcie3_rc: pcie@2930000 { >>>           compatible = "ti,j721e-pcie-host"; >>>           reg = <0x00 0x02930000 0x00 0x1000>, >>> @@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 { >>>           dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; >>>       }; >>> -    pcie3_ep: pcie-ep@2930000 { >>> -        compatible = "ti,j721e-pcie-ep"; >>> -        reg = <0x00 0x02930000 0x00 0x1000>, >>> -              <0x00 0x02937000 0x00 0x400>, >>> -              <0x00 0x0e800000 0x00 0x00800000>, >>> -              <0x44 0x10000000 0x00 0x08000000>; >>> -        reg-names = "intd_cfg", "user_cfg", "reg", "mem"; >>> -        interrupt-names = "link_state"; >>> -        interrupts = ; >>> -        ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; >>> -        max-link-speed = <3>; >>> -        num-lanes = <2>; >>> -        power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; >>> -        clocks = <&k3_clks 242 1>; >>> -        clock-names = "fck"; >>> -        max-functions = /bits/ 8 <6>; >>> -        max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; >>> -        dma-coherent; >>> -        #address-cells = <2>; >>> -        #size-cells = <2>; >>> -    }; >>> - >>>       serdes_wiz4: wiz@5050000 { >>>           compatible = "ti,am64-wiz-10g"; >>>           #address-cells = <1>; >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts >>> b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts >>> index f650a7fd66b4..07d3282a583b 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts >>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts >>> @@ -896,35 +896,11 @@ &pcie2_rc { >>>       status = "disabled"; >>>   }; >>> -&pcie0_ep { >>> -    status = "disabled"; >>> -    phys = <&serdes0_pcie_link>; >>> -    phy-names = "pcie-phy"; >>> -    num-lanes = <1>; >>> -}; >>> - >>> -&pcie1_ep { >>> -    status = "disabled"; >>> -    phys = <&serdes1_pcie_link>; >>> -    phy-names = "pcie-phy"; >>> -    num-lanes = <2>; >>> -}; >>> - >>> -&pcie2_ep { >>> -    /* Unused */ >>> -    status = "disabled"; >>> -}; >>> - >>>   &pcie3_rc { >>>       /* Unused */ >>>       status = "disabled"; >>>   }; >>> -&pcie3_ep { >>> -    /* Unused */ >>> -    status = "disabled"; >>> -}; >>> - >>>   &icssg0_mdio { >>>       status = "disabled"; >>>   };