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Date:   Tue, 6 Jun 2023 06:19:29 -0700
From:   Isaku Yamahata <isaku.yamahata@gmail.com>
To:     Yuan Yao <yuan.yao@linux.intel.com>
Cc:     isaku.yamahata@intel.com, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com,
        Paolo Bonzini <pbonzini@redhat.com>, erdemaktas@google.com,
        Sean Christopherson <seanjc@google.com>,
        Sagi Shahar <sagis@google.com>,
        David Matlack <dmatlack@google.com>,
        Kai Huang <kai.huang@intel.com>,
        Zhi Wang <zhi.wang.linux@gmail.com>, chen.bo@intel.com,
        Sean Christopherson <sean.j.christopherson@intel.com>
Subject: Re: [PATCH v14 031/113] KVM: x86/mmu: Replace hardcoded value 0 for
 the initial value for SPTE
Message-ID: <20230606131929.GA2403361@ls.amr.corp.intel.com>
References: <cover.1685333727.git.isaku.yamahata@intel.com>
 <8b4f21e2fada944d041ffee0f27d527e0e447cbb.1685333727.git.isaku.yamahata@intel.com>
 <20230606045923.ol5kjhagiimqksmn@yy-desk-7060>
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On Tue, Jun 06, 2023 at 12:59:23PM +0800,
Yuan Yao <yuan.yao@linux.intel.com> wrote:

> On Sun, May 28, 2023 at 09:19:13PM -0700, isaku.yamahata@intel.com wrote:
> > From: Isaku Yamahata <isaku.yamahata@intel.com>
> >
> > The TDX support will need the "suppress #VE" bit (bit 63) set as the
> > initial value for SPTE.  To reduce code change size, introduce a new macro
> > SHADOW_NONPRESENT_VALUE for the initial value for the shadow page table
> > entry (SPTE) and replace hard-coded value 0 for it.  Initialize shadow page
> > tables with their value.
> >
> > The plan is to unconditionally set the "suppress #VE" bit for both AMD and
> > Intel as: 1) AMD hardware uses the bit 63 as NX for present SPTE and
> > ignored for non-present SPTE; 2) for conventional VMX guests, KVM never
> > enables the "EPT-violation #VE" in VMCS control and "suppress #VE" bit is
> > ignored by hardware.
> >
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> > Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
> > ---
> >  arch/x86/kvm/mmu/mmu.c         | 20 +++++++++++++++-----
> >  arch/x86/kvm/mmu/paging_tmpl.h |  2 +-
> >  arch/x86/kvm/mmu/spte.h        |  2 ++
> >  arch/x86/kvm/mmu/tdp_mmu.c     | 14 +++++++-------
> >  4 files changed, 25 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> > index dc2b9a2f717c..1b6fd4434e96 100644
> > --- a/arch/x86/kvm/mmu/mmu.c
> > +++ b/arch/x86/kvm/mmu/mmu.c
> > @@ -576,9 +576,9 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
> >
> >  	if (!is_shadow_present_pte(old_spte) ||
> >  	    !spte_has_volatile_bits(old_spte))
> > -		__update_clear_spte_fast(sptep, 0ull);
> > +		__update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
> >  	else
> > -		old_spte = __update_clear_spte_slow(sptep, 0ull);
> > +		old_spte = __update_clear_spte_slow(sptep, SHADOW_NONPRESENT_VALUE);
> >
> >  	if (!is_shadow_present_pte(old_spte))
> >  		return old_spte;
> > @@ -612,7 +612,7 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
> >   */
> >  static void mmu_spte_clear_no_track(u64 *sptep)
> >  {
> > -	__update_clear_spte_fast(sptep, 0ull);
> > +	__update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
> >  }
> >
> >  static u64 mmu_spte_get_lockless(u64 *sptep)
> > @@ -1969,7 +1969,8 @@ static bool kvm_sync_page_check(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
> >
> >  static int kvm_sync_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, int i)
> >  {
> > -	if (!sp->spt[i])
> > +	/* sp->spt[i] has initial value of shadow page table allocation */
> > +	if (sp->spt[i] != SHADOW_NONPRESENT_VALUE)
> 
> This should be "sp->spt[i] == SHADOW_NONPRESENT_VALUE" ? Looks all present spt[i]
> are skipped without sync for shadow paging.

Oop, you're right. Will fix it.

Thanks,
-- 
Isaku Yamahata <isaku.yamahata@gmail.com>