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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PA4PR03MB7136.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c5473357-8a86-4ffb-e1c4-08db66aa37ad X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jun 2023 16:22:26.7665 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UaygiOUzVy05/8O2bc3Bpynx1UNX745EWSgdNz51fbuVLlndroc1I5+BxgWttzLuuQDnk48sGll409EtBhbT/KLWhPDVb44SLlSTAh3Gslc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR03MB8708 X-Proofpoint-GUID: RFMnEgtMefOGSjPO6Et3TNmK4SFe8XD3 X-Proofpoint-ORIG-GUID: RFMnEgtMefOGSjPO6Et3TNmK4SFe8XD3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-06_12,2023-06-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=999 adultscore=0 spamscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 clxscore=1011 lowpriorityscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306060140 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This Patch series is intended to introduce the potential generic driver for pin controls over SCMI protocol, provided in the latest beta version of DEN= 0056 [0]. On ARM-based systems, a separate Cortex-M based System Control Processor (S= CP) provides control on pins, as well as with power, clocks, reset controllers.= In this case, kernel should use one of the possible transports, described in [0] to acces= s SCP and control clocks/power-domains etc. This driver is using SMC transport to com= municate with SCP via SCMI protocol and access to the Pin Control Subsystem. The provided driver consists of 2 parts: - firmware/arm_scmi/pinctrl.c - the SCMI pinctrl protocol inmplementation responsible for the communication with SCP firmware. - drivers/pinctrl/pinctrl-scmi.c - pinctrl driver, which is using pinctrl protocol implementation to access all necessary data. Configuration: The scmi-pinctrl driver can be configured using DT bindings. For example: / { cpu_scp_shm: scp-shmem@0x53FF0000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x53FF0000 0x0 0x1000>; }; firmware { scmi { compatible =3D "arm,scmi-smc"; arm,smc-id =3D <0x82000002>; shmem =3D <&cpu_scp_shm>; #address-cells =3D <1>; #size-cells =3D <0>; scmi_pinctrl: protocol@19 { reg =3D <0x18>; #pinctrl-cells =3D <0>; i2c2_pins: i2c2 { groups =3D "i2c2_a"; function =3D "i2c2"; }; }; }; }; }; &pfc { /delete-node/i2c2; }; So basically, it's enough to move pfc subnode, which configures pin group t= hat should work through SCMI protocol to scmi_pinctrl node. The current driver implementation is us= ing generic pinctrl dt_node format. I've tested this driver on the Renesas H3ULCB Kingfisher board with pinctrl= driver ported to the Arm-trusted-firmware. Unfortunately, not all hardware was possible to test = because the Renesas pinctrl driver has gaps in pins and groups numeration, when Spec [0] requir= es pins, groups and functions numerations to be 0..n without gaps. Also, sharing link to the ATF pinctrl driver I used for testing: https://github.com/oleksiimoisieiev/arm-trusted-firmware/tree/pinctrl_rcar_= m3_up [0] https://developer.arm.com/documentation/den0056/latest --- Changes v2 -> v3: - update get_name calls as suggested by Cristian Marussi - fixing comments - refactoring of the dt_bindings according to the comments Changes v1 -> v2: - rebase patches to the latest kernel version - use protocol helpers in the pinctrl scmi protocol driver implementatio= n - reworked pinctrl_ops. Removed similar calls to simplify the interface - implementation of the .instance_deinit callback to properly clean reso= urces - add description of the pinctrl protocol to the device-tree schema --- Oleksii Moisieiev (4): firmware: arm_scmi: Add optional flags to extended names helper firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support pinctrl: Implementation of the generic scmi-pinctrl driver dt-bindings: firmware: arm,scmi: Add support for pinctrl protocol .../bindings/firmware/arm,scmi.yaml | 53 ++ MAINTAINERS | 7 + drivers/firmware/arm_scmi/Makefile | 2 +- drivers/firmware/arm_scmi/clock.c | 2 +- drivers/firmware/arm_scmi/driver.c | 10 +- drivers/firmware/arm_scmi/perf.c | 3 +- drivers/firmware/arm_scmi/pinctrl.c | 836 ++++++++++++++++++ drivers/firmware/arm_scmi/power.c | 2 +- drivers/firmware/arm_scmi/powercap.c | 2 +- drivers/firmware/arm_scmi/protocols.h | 4 +- drivers/firmware/arm_scmi/reset.c | 3 +- drivers/firmware/arm_scmi/sensors.c | 2 +- drivers/firmware/arm_scmi/voltage.c | 2 +- drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-scmi.c | 554 ++++++++++++ include/linux/scmi_protocol.h | 47 + 17 files changed, 1530 insertions(+), 11 deletions(-) create mode 100644 drivers/firmware/arm_scmi/pinctrl.c create mode 100644 drivers/pinctrl/pinctrl-scmi.c --=20 2.25.1