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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u27-20020a63b55b000000b00543a4c47eb6si4231863pgo.820.2023.06.06.10.09.17; Tue, 06 Jun 2023 10:09:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b=fgwjx5hW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238221AbjFFQzH (ORCPT + 99 others); Tue, 6 Jun 2023 12:55:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238386AbjFFQyu (ORCPT ); Tue, 6 Jun 2023 12:54:50 -0400 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 900E610F7; Tue, 6 Jun 2023 09:54:46 -0700 (PDT) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 896615FD54; Tue, 6 Jun 2023 19:54:44 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1686070484; bh=Z3E+qqaUAGaWeT5IbR6dVGiBQMvs+bk43lDEXzhVAAM=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=fgwjx5hWc0N6KD5F2kmUMsEI66q9ktsm4bEQsZ+iks1z7gfXBQG2tNEnz1Pq8KI78 1Pn2/Q9VxsdRutm+UetCUiAHpBYdE8xOT2DdqzQncNCn+oIHBOvT+zPxuyMOMgrFKP 5yEyxKWOLB3uC6ADDK8eW+atxanhPzx96iMfStYjJd5U64zQ7gADzrfEZSjNmiRhfm 181PB9c3UsYX1wiIXYJ/E8iYowHM66h9QxyfpPpYK9zQaS/VBVumepUU9/nJrj5vGi zPtKSyUSHf3PvOKDfgGMHOVjivk67q1cWKg+ANHSbdMzdFvpfeVgYQQp4ueFKaM7Wr B/ZODUZrKU07g== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Tue, 6 Jun 2023 19:54:42 +0300 (MSK) From: George Stark To: , , , , , , , , CC: , , , , , George Stark Subject: [PATCH v3] meson saradc: fix clock divider mask length Date: Tue, 6 Jun 2023 19:53:57 +0300 Message-ID: <20230606165357.42417-1-gnstark@sberdevices.ru> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH01.sberdevices.ru (172.16.1.4) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2023/06/06 14:43:00 #21444531 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to datasheets of supported meson SOCs length of ADC_CLK_DIV field is 6 bits long. Although all supported SOCs have the register with that field documented later SOCs use external clock rather than ADC internal clock so this patch affects only meson8 family (S8* SOCs) Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs") Signed-off-by: George Stark --- Changelog: v1 -> v2: * Update commit message v2 -> v3: * Update commit message --- drivers/iio/adc/meson_saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 85b6826cc10c..b93ff42b8c19 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -72,7 +72,7 @@ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) -- 2.38.4