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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fy2-20020a17090b020200b0025998ebdc4csi1573150pjb.60.2023.06.06.12.04.48; Tue, 06 Jun 2023 12:05:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239174AbjFFS6I (ORCPT + 99 others); Tue, 6 Jun 2023 14:58:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231895AbjFFS6B (ORCPT ); Tue, 6 Jun 2023 14:58:01 -0400 Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [IPv6:2001:4b7a:2000:18::169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9952110F0 for ; Tue, 6 Jun 2023 11:57:58 -0700 (PDT) Received: from SoMainline.org (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 5DD383F79F; Tue, 6 Jun 2023 20:57:53 +0200 (CEST) Date: Tue, 6 Jun 2023 20:57:51 +0200 From: Marijn Suijten To: Kuogee Hsieh Cc: robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, dianders@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, airlied@gmail.com, agross@kernel.org, dmitry.baryshkov@linaro.org, andersson@kernel.org, quic_abhinavk@quicinc.com, quic_jesszhan@quicinc.com, quic_sbillaka@quicinc.com, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v16] drm/msm/dpu: add DSC blocks to the catalog of MSM8998 and SC8180X Message-ID: References: <1686076299-11504-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1686076299-11504-1-git-send-email-quic_khsieh@quicinc.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023-06-06 11:31:39, Kuogee Hsieh wrote: > From: Abhinav Kumar > > Some platforms have DSC blocks which have not been declared in the catalog. > Complete DSC 1.1 support for all platforms by adding the missing blocks to > MSM8998 and SC8180X. Still a NACK, as pointed out in v15 both the title and this commit description point to SC8180X but that catalog entry is not touched at all anymore after rebasing on top of f5abecfe339e4 ("drm/msm/dpu: enable DSPP and DSC on sc8180x"). - Marijn > > Changes in v9: > -- add MSM8998 and SC8180x to commit title > > Changes in v10: > -- fix grammar at commit text > > Changes in v12: > -- fix "titil" with "title" at changes in v9 > > Changes in v14: > -- "dsc" tp "DSC" at commit title > > Changes in v15: > -- fix merge conflicts at dpu_5_1_sc8180x.h > > Changes in v16 > -- fix cherry-pick error by deleting both redundant .dsc and .dsc_count > assignment from dpu_5_1_sc8180x.h > > Signed-off-by: Abhinav Kumar > Reviewed-by: Dmitry Baryshkov > Reviewed-by: Marijn Suijten > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > index 3c732a0..7d0d0e7 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > @@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > }; > > +static const struct dpu_dsc_cfg msm8998_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), > + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), > +}; > + > static const struct dpu_dspp_cfg msm8998_dspp[] = { > DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, > &msm8998_dspp_sblk), > @@ -199,6 +204,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { > .dspp = msm8998_dspp, > .pingpong_count = ARRAY_SIZE(msm8998_pp), > .pingpong = msm8998_pp, > + .dsc_count = ARRAY_SIZE(msm8998_dsc), > + .dsc = msm8998_dsc, > .intf_count = ARRAY_SIZE(msm8998_intf), > .intf = msm8998_intf, > .vbif_count = ARRAY_SIZE(msm8998_vbif), > -- > 2.7.4 >