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References: <20230606165357.42417-1-gnstark@sberdevices.ru>
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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Tue, 6 Jun 2023 21:14:29 +0200
Message-ID: <CAFBinCBzrXpfzNb9COVHg13uCmXTBhnS6YLVyFR=YCkj9v-ypg@mail.gmail.com>
Subject: Re: [PATCH v3] meson saradc: fix clock divider mask length
To:     George Stark <gnstark@sberdevices.ru>
Cc:     jic23@kernel.org, lars@metafoo.de, neil.armstrong@linaro.org,
        khilman@baylibre.com, jbrunet@baylibre.com,
        andriy.shevchenko@linux.intel.com, nuno.sa@analog.com,
        linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
        kernel@sberdevices.ru
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Thank you George!

On Tue, Jun 6, 2023 at 6:54=E2=80=AFPM George Stark <gnstark@sberdevices.ru=
> wrote:
>
> According to datasheets of supported meson SOCs length of ADC_CLK_DIV
> field is 6 bits long. Although all supported SOCs have the register
> with that field documented later SOCs use external clock rather than
> ADC internal clock so this patch affects only meson8 family (S8* SOCs)
>
> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Aml=
ogic Meson SoCs")
> Signed-off-by: George Stark <GNStark@sberdevices.ru>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>