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Date:   Wed, 7 Jun 2023 11:05:21 +1000
From:   Stephen Rothwell <sfr@canb.auug.org.au>
To:     Christoffer Dall <cdall@cs.columbia.edu>,
        Marc Zyngier <maz@kernel.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will@kernel.org>
Cc:     Joey Gouly <joey.gouly@arm.com>,
        Kristina Martsenko <kristina.martsenko@arm.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux Next Mailing List <linux-next@vger.kernel.org>,
        Oliver Upton <oliver.upton@linux.dev>
Subject: Re: linux-next: manual merge of the kvm-arm tree with the arm64
 tree
Message-ID: <20230607110521.442280f9@canb.auug.org.au>
In-Reply-To: <20230606114927.227a66a5@canb.auug.org.au>
References: <20230606114927.227a66a5@canb.auug.org.au>
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Hi all,

On Tue, 6 Jun 2023 11:49:27 +1000 Stephen Rothwell <sfr@canb.auug.org.au> w=
rote:
>
> Today's linux-next merge of the kvm-arm tree got a conflict in:
>=20
>   arch/arm64/kernel/cpufeature.c
>=20
> between commits:
>=20
>   b7564127ffcb ("arm64: mops: detect and enable FEAT_MOPS")
>   c1fa32c8f189 ("arm64: cpufeature: add TCR2 cpucap")
>   b5a8e35236ee ("arm64: cpufeature: add Permission Indirection Extension =
cpucap")
>=20
> from the arm64 tree and commit:
>=20
>   c876c3f182a5 ("KVM: arm64: Relax trapping of CTR_EL0 when FEAT_EVT is a=
vailable")
>=20
> from the kvm-arm tree.
>=20
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.

Commit b5a8e35236ee changed a bit, so the new resolution is below.
--=20
Cheers,
Stephen Rothwell

diff --cc arch/arm64/kernel/cpufeature.c
index c3bdb14bb4bd,4a2ab3f366de..000000000000
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -2662,27 -2641,17 +2662,38 @@@ static const struct arm64_cpu_capabilit
  		.cpu_enable =3D cpu_enable_dit,
  		ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
  	},
 +	{
 +		.desc =3D "Memory Copy and Memory Set instructions",
 +		.capability =3D ARM64_HAS_MOPS,
 +		.type =3D ARM64_CPUCAP_SYSTEM_FEATURE,
 +		.matches =3D has_cpuid_feature,
 +		.cpu_enable =3D cpu_enable_mops,
 +		ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
 +	},
 +	{
 +		.capability =3D ARM64_HAS_TCR2,
 +		.type =3D ARM64_CPUCAP_SYSTEM_FEATURE,
 +		.matches =3D has_cpuid_feature,
 +		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
 +	},
 +	{
 +		.desc =3D "Stage-1 Permission Indirection Extension (S1PIE)",
 +		.capability =3D ARM64_HAS_S1PIE,
 +		.type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE,
 +		.matches =3D has_cpuid_feature,
 +		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP)
 +	},
+ 	{
+ 		.desc =3D "Enhanced Virtualization Traps",
+ 		.capability =3D ARM64_HAS_EVT,
+ 		.type =3D ARM64_CPUCAP_SYSTEM_FEATURE,
+ 		.sys_reg =3D SYS_ID_AA64MMFR2_EL1,
+ 		.sign =3D FTR_UNSIGNED,
+ 		.field_pos =3D ID_AA64MMFR2_EL1_EVT_SHIFT,
+ 		.field_width =3D 4,
+ 		.min_field_value =3D ID_AA64MMFR2_EL1_EVT_IMP,
+ 		.matches =3D has_cpuid_feature,
+ 	},
  	{},
  };
 =20

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