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In-Reply-To: <01dae949-4018-37f4-2dd9-cbecbd65b9a1@linaro.org>
From:   Fabrizio Lamarque <fl.scratchpad@gmail.com>
Date:   Wed, 7 Jun 2023 09:40:58 +0200
Message-ID: <CAPJMGm6T7ckH-W_DZu+7ySp3pOuKpe-MZPnvcfOz1wBJyG-pJg@mail.gmail.com>
Subject: Re: [PATCH v3 5/5] dt-bindings: iio: ad7192: Allow selection of clock modes
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc:     Conor Dooley <conor@kernel.org>, jic23@kernel.org,
        Lars-Peter Clausen <lars@metafoo.de>,
        Michael Hennerich <Michael.Hennerich@analog.com>,
        Alexandru Tachici <alexandru.tachici@analog.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>, linux-iio@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
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On Wed, May 31, 2023 at 9:24=E2=80=AFPM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 31/05/2023 11:40, Fabrizio Lamarque wrote:
> > On Wed, May 31, 2023 at 9:14=E2=80=AFAM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 31/05/2023 08:59, Fabrizio Lamarque wrote:
> >>> On Tue, May 30, 2023 at 7:22=E2=80=AFPM Conor Dooley <conor@kernel.or=
g> wrote:
> >>>>
> >>>> On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wr=
ote:
> >>>>> From: Fabrizio Lamarque <fl.scratchpad@gmail.com>
> >>>>>
> >>>>> AD7192 supports external clock sources, generated by a digital cloc=
k
> >>>>> source or a crystal oscillator, or internally generated clock optio=
n
> >>>>> without external components.
> >>>>>
> >>>>> Describe choice between internal and external clock, crystal or ext=
ernal
> >>>>> oscillator, and internal clock output enable.
> >>>>>
> >>>>> Signed-off-by: Fabrizio Lamarque <fl.scratchpad@gmail.com>
> >>>>> ---
> >>>>>  .../bindings/iio/adc/adi,ad7192.yaml          | 27 +++++++++++++++=
+---
> >>>>>  1 file changed, 24 insertions(+), 3 deletions(-)
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.y=
aml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> >>>>> index 16def2985ab4..f7ecfd65ad80 100644
> >>>>> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> >>>>> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> >>>>> @@ -32,7 +32,8 @@ properties:
> >>>>>
> >>>>>    clocks:
> >>>>>      maxItems: 1
> >>>>> -    description: phandle to the master clock (mclk)
> >>>>> +    description: |
> >>>>> +      Master clock (mclk). If not set, internal clock is used.
> >>>>>
> >>>>>    clock-names:
> >>>>>      items:
> >>>>> @@ -50,6 +51,17 @@ properties:
> >>>>>    vref-supply:
> >>>>>      description: VRef voltage supply
> >>>>>
> >>>>> +  adi,clock-xtal:
> >>>>> +    description: |
> >>>>> +      Select whether an external crystal oscillator or an external
> >>>>> +      clock is applied as master (mclk) clock.
> >>>>> +    type: boolean
> >>>>
> >>>> Am I being daft, or are these the same thing? If they are not, and u=
se
> >>>> different input pins, I think it should be explained as it not clear=
.
> >>>> Could you explain why we actually care that the source is a xtal ver=
sus
> >>>> it being mclk, and why just having master clock is not sufficient?
> >>>
> >>> I may revise the description as follows. Feel free to add your sugges=
tions
> >>> in case it is still not clear enough.
> >>>
> >>> "Select whether an external crystal oscillator between MCLK1 and MCLK=
2 or
> >>> an external CMOS-compatible clock on MCLK2 is used as master clock".
> >>>
> >>> This is used to properly set CLK0 and CLK1 bits in the MODE register.
> >>> I guess most applications would use an external crystal or internal c=
lock.
> >>> The external digital clock would allow synchronization of multiple AD=
Cs,
> >>
> >> Description confuses me. Why would it matter what type of clock you ha=
ve
> >> as input - external crystal oscillator or external CMOS-compatible
> >> clock? Later you refer to "internal", so maybe you meant here also
> >> internal for one of the options?
> >
> > The AD7192 needs to be configured according to the type of external
> > clock that is
> > applied on MCLK1/MCLK2 pins in order to activate the correct circuitry.
> >
> > Here are some citations from the datasheet:
> >
> > MCLK2 pin description:
> > "The AD7192 has an internal 4.92 MHz clock. This internal clock can be
> > made available
> > on the MCLK2 pin. The clock for the AD7192 can be provided externally
> > also in the form
> > of a crystal or external clock. A crystal can be tied across the MCLK1
> > and MCLK2 pins.
> > Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock=
 and the
> > MCLK1 pin left unconnected."
> >
> > Each of these clock modes have to be configured via AD7192 mode registe=
r.
> > (Clock source configuration bits, mode register, CLK0 and CLK1).
> > Here is their description from datasheet:
> >
> > "Either the on-chip 4.92 MHz clock or an external clock can be used.
> > The ability to
> > use an external clock allows several AD7192 devices to be synchronized.=
 Also,
> > 50 Hz/60 Hz rejection is improved when an accurate external clock
> > drives the AD7192."
> >
> > The choice between internal clock, external crystal oscillator or
> > external CMOS digital
> > clock is a decision of the HW designer driven by noise rejection,
> > synchronization, and
> > cost requirements.
> >
> > If possible, I kindly ask you suggestions on how to adjust the descript=
ion
> > so that it would be cleaner.
>
> It's fine. I missed that part that first option requires feeding the
> clock through two pins ("and").

Thank you once again.
I've reworded the commit message, removed the
adi,int-clock-output-enable option and clarified the adi,clock-xtal
entry.

This would be the new commit message:

AD7192 can be clocked from either:
 - Internal clock
 - CMOS-compatible clock on MCLK2
 - Crystal oscillator on MCLK1 and MCLK2

Each of these modes have to be configured via AD7192 mode register.
Describe choice between these clock modes.


And this is the new description for adi,clock-xtal:

This bit sets external clock mode. When set, master clock is sourced from
a crystal connected from MCLK1 to MCLK2.
When cleared, a CMOS-compatible clock source is expected on MCLK2.


Is this description cleaner? If possible, I kindly ask you for feedback bef=
ore
posting a v4 (with only patch 3/5 and 5/5 since the others have
already been applied).

Best regards,
Fabrizio Lamarque