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From:   "Paller, Kim Seer" <KimSeer.Paller@analog.com>
To:     Jonathan Cameron <Jonathan.Cameron@Huawei.com>
CC:     Jonathan Cameron <jic23@kernel.org>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2 2/2] iio: adc: max14001: New driver
Thread-Topic: [PATCH v2 2/2] iio: adc: max14001: New driver
Thread-Index: AQHZl67Y+VuDoLqrgE+gZ2yoOVHpUq982k+AgAA5dsCAAMU+AIABVP+Q
Date:   Wed, 7 Jun 2023 11:17:33 +0000
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> -----Original Message-----
> From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
> Sent: Tuesday, June 6, 2023 6:36 PM
> To: Paller, Kim Seer <KimSeer.Paller@analog.com>
> Cc: Jonathan Cameron <jic23@kernel.org>; lars@metafoo.de;
> krzysztof.kozlowski@linaro.org; broonie@kernel.org; lgirdwood@gmail.com;
> linux-iio@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 2/2] iio: adc: max14001: New driver
> 
> [External]
> 
> 
> 
> > >
> > > > +	struct mutex		lock;
> > > > +	struct regmap		*regmap;
> > > > +	int			vref_mv;
> > > > +	/*
> > > > +	 * DMA (thus cache coherency maintenance) requires the
> > > > +	 * transfer buffers to live in their own cache lines.
> > >
> > > You are looking at an old kernel I guess - we fixed all of these - and
> > > introduced IIO_DMA_MINALIGN for __aligned(IIO_DMA_MINALIGN) to
> > > make it easier to fix any such problems in future.
> > >
> > > Upshot is that ___cacheline_aligned aligns to the l1 cacheline length.
> > > Some fun systems (such as the big servers I use in my dayjob) have higher
> > > cacheline sizes for their larger / further from CPU caches.
> > > One group of SoCs out there is known to both do non coherent DMA and
> > > have a larger line size for the bit relevant to that than ___cacheline_aligned
> > > gives you. So on that rare platform this is currently broken.
> >
> > It's good to know. Given this information, is there anything specific that I
> > need to change in the code or implementation related to
> > the ___cacheline_aligned part?
> 
> Replace it with __aligned(IIO_DMA_MINALIGN) as has hopefully now been
> done
> in all upstream drivers.

When I attempted to implement this change, I encountered a checkpatch warning 
in the latest kernel version. The warning indicated that externs should be avoided 
in .c files and emphasized the need for an identifier name for the function 
definition argument 'IIO_DMA_MINALIGN'. I attempted to define a macro with an 
appropriate identifier name, but I still received the same checkpatch warning. 
It's possible that I may have overlooked something in my approach. I would 
appreciate your thoughts and insights on this matter. Thanks.

> 
> > >
> 
> > > > +}
> > > > +
> > > > +static int max14001_reg_update(struct max14001_state *st,
> > > > +				unsigned int reg_addr,
> > > > +				unsigned int mask,
> > > > +				unsigned int val)
> > > > +{
> > > > +	int ret;
> > > > +
> > > > +	/* Enable SPI Registers Write */
> > > > +	ret = max14001_write(st, MAX14001_WEN,
> > > MAX14001_WRITE_WEN);
> > >
> > > Mixing regmap and non regmap rather defeats the point of having a
> standard
> > > interface.  Use regmap_read and regmap_write throughout or not at all.
> >
> > I found it difficult to implement the regmap interface due to the timing
> diagram
> > requirements. The chip select needs to be changed between transfers, which,
> > as far as I know, does not work with regmap. Perhaps, I will consider sticking
> > to the non-regmap approach.
> 
> That may be sensible if there are odd requirements or just call regmap_write()
> which will call your max14001_write() anyway and opencode the timing
> requirements etc by multiple remap calls.  Obviously benefits of regmap
> reduced
> though so may not be worth bothering unless it is worth using the caching or
> similar.
> 
> Jonathan
> 
>