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[2003:e4:1f30:5300:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id c8-20020a170906924800b00977cc473b41sm5157196ejx.142.2023.06.07.08.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jun 2023 08:57:41 -0700 (PDT) Date: Wed, 7 Jun 2023 17:57:39 +0200 From: Thierry Reding To: Peter De Schrijver Cc: jonathanh@nvidia.com, mperttunen@nvidia.com, sudeep.holla@arm.com, talho@nvidia.com, robh@kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, stefank@nvidia.com, krzysztof.kozlowski@linaro.org Subject: Re: [PATCH v4 6/6] firmware: tegra: bpmp: Add support for DRAM MRQ GSCs Message-ID: References: <20230511132048.1122075-1-pdeschrijver@nvidia.com> <20230511132048.1122075-7-pdeschrijver@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="gObwIVTIUUFZASFm" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.10 (2023-03-25) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --gObwIVTIUUFZASFm Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, May 16, 2023 at 12:55:03PM +0300, Peter De Schrijver wrote: > On Tue, May 16, 2023 at 11:35:24AM +0200, Thierry Reding wrote: > > On Thu, May 11, 2023 at 04:20:51PM +0300, Peter De Schrijver wrote: > > > Implement support for DRAM MRQ GSCs. > > >=20 > > > Signed-off-by: Peter De Schrijver > > > --- > > > drivers/firmware/tegra/bpmp-tegra186.c | 232 ++++++++++++++++++-----= -- > > > drivers/firmware/tegra/bpmp.c | 4 +- > > > 2 files changed, 168 insertions(+), 68 deletions(-) > > >=20 > > > diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmwar= e/tegra/bpmp-tegra186.c > > > index 2e26199041cd..74575c9f0014 100644 > > > --- a/drivers/firmware/tegra/bpmp-tegra186.c > > > +++ b/drivers/firmware/tegra/bpmp-tegra186.c > > > @@ -4,7 +4,9 @@ > > > */ > > > =20 > > > #include > > > +#include > > > #include > > > +#include > > > #include > > > =20 > > > #include > > > @@ -13,12 +15,21 @@ > > > =20 > > > #include "bpmp-private.h" > > > =20 > > > +enum tegra_bpmp_mem_type { TEGRA_INVALID, TEGRA_SRAM, TEGRA_DRAM }; > >=20 > > Still not convinced about this one. > >=20 > > > + > > > struct tegra186_bpmp { > > > struct tegra_bpmp *parent; > > > =20 > > > struct { > > > - struct gen_pool *pool; > > > - void __iomem *virt; > > > + union { > > > + struct { > > > + void __iomem *virt; > > > + struct gen_pool *pool; > > > + } sram; > > > + struct { > > > + void *virt; > > > + } dram; > > > + }; > >=20 > > The drawback of these unions is that they can lead to ambiguity, so you > > need the tegra_bpmp_mem_type enum to differentiate between the two. > >=20 >=20 > No, on the contrary, now it's clear you can either have void __iomem * > and struct gen_pool * or void *virt but not both. No, it's not clear. You can have one part of your driver write the sram.virt field and another read dram.virt and they'll end up pointing at the same memory location but with different meaning. That's why you need to introduce the enumeration in order to specify which one of the two you want to pick. And that's exactly where you start introducing the potential for inconsistency: now you need to be extra careful that the enumeration and the unions are set correctly. You effectively have two sources of truth and they don't necessarily match. You can also end up (at least theoretically) with the invalid value, so you need an extra check for that too. You can avoid all of those inconsistencies if you reduce this to one source of truth, namely the pointers that you're going to use. Your variant would be slightly better if you omitted the invalid value because then you could still have an internal inconsistency, but the likelihood is much reduced. > > If you change this to something like: > >=20 > > struct { > > struct gen_pool *pool; > > void __iomem *sram; > > void *dram; > > dma_addr_t phys; > > } tx, rx; > >=20 > > you eliminate all ambiguity because you can either have pool and sram > > set, or you can have dram set, and depending on which are set you know > > which type of memory you're dealing with. > >=20 >=20 > No. You just add ambiguity. It's not clear from looking at the data > structure which fields are valid for which case. That's easily fixed by adding comments explaining what you use them for. But the code should make that pretty clear already. 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