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Wed, 7 Jun 2023 17:18:55 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup Date: Wed, 7 Jun 2023 17:16:35 -0500 Message-ID: <20230607221651.2454764-11-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230607221651.2454764-1-terry.bowman@amd.com> References: <20230607221651.2454764-1-terry.bowman@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001506:EE_|LV2PR12MB5895:EE_ X-MS-Office365-Filtering-Correlation-Id: 2655bd4c-4ee4-477b-b336-08db67a52f59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 74VWK9tqw56iT8TYJFWoZPkNspSimgGTf3Nq97UbQpA8MYRd4t42iqKA9kCCR0KXrWHO+CdTuTRLkip3O/YYRiUqQVO+e/eAawwGUsP2cflVF0XEv6dbOiWx7A/inXvlPHIYnmsHkn3OMLYSPI7XcBmroFQCVGCb249HMg1R5Na0DTogKYDAzgHjHSzpxjEdCWlGLth/i3KYvkNObLonP0E9wSTikGzskj2GLLGCJmuV02FbXMjbbxP0JPVv51AsWU82qmK2WtJVlcVk1ddy+41gfrHoRnBhxLwDU0Yl7JAnMW8dEepzjI+O9fhpqRGUZIuCmbeXa+N7AZgjqgdMgQ9gkww4e8OaIWvRoKBjfXYPXZ4VuXocLlW5E15ZnzJvdOTB0R2bMhTw+18AwACkd7JtpWV6sIHYfRwB2Ml3AcEpY0m+Zxom09d3yWJX74EFXqmQ+NyCZ+JF2AJ1/Ae1UFx/OdOQ3AC1PDgi1lwOtMppty5iRWe03e4SnKxGeW6/RkQP4f4ZhRv7pYbU22ZSvNyZpswoSPrR4uHfs6gNt/4iOpT8GXWYOoo7FvuP9MryzJAB8K/kqhVk+GQbUwwm9qOFEnXoVfAe7n2XQmGdV57DfWCmyJZhmobLcNbBOCgnuyA/nLfgnZfhka4vu7ZshOOHtAGuVye689Tkxp68sZapqZFPDil4A4diOEc+2Jv5xPOoIdZ44tSyTGx6CoHQqMqms7qzRXYgsHWb4UH98UH68hbtVAmzFWwv5MN+iQL9D7YS3oxlyWq/Id6zNtwy4A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199021)(36840700001)(40470700004)(46966006)(2616005)(8936002)(8676002)(16526019)(186003)(41300700001)(2906002)(5660300002)(44832011)(26005)(47076005)(1076003)(336012)(83380400001)(7416002)(426003)(7696005)(40480700001)(36860700001)(40460700003)(478600001)(316002)(110136005)(54906003)(6666004)(356005)(70206006)(81166007)(82740400003)(82310400005)(86362001)(70586007)(36756003)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 22:18:56.4104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2655bd4c-4ee4-477b-b336-08db67a52f59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001506.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5895 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Robert Richter In order to move the RCH dport component register setup to cxl_pci the base address must be stored in CXL device state (cxlds) for both modes, RCH and VH. Store it in cxlds->component_reg_phys and use it for endpoint creation. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman --- drivers/cxl/mem.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 43ecd150bdc7..a34d6560c25c 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -51,7 +51,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_port *parent_port = parent_dport->port; struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_port *endpoint, *iter, *down; - resource_size_t component_reg_phys; int rc; /* @@ -72,12 +71,12 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, * typical register locator mechanism. */ if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE) - component_reg_phys = + cxlds->component_reg_phys = cxl_probe_rcrb(&cxlmd->dev, parent_dport->rcrb.base, NULL, CXL_RCRB_UPSTREAM); - else - component_reg_phys = cxlds->component_reg_phys; - endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys, + + endpoint = devm_cxl_add_port(host, &cxlmd->dev, + cxlds->component_reg_phys, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint); -- 2.34.1