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Thu, 8 Jun 2023 01:55:45 +0000 Date: Wed, 7 Jun 2023 18:55:39 -0700 From: Ashok Raj To: Borislav Petkov CC: X86 ML , LKML , Dave Hansen , Thomas Gleixner , Ashok Raj Subject: Re: [PATCH 2/2] x86/microcode: Add a "microcode=" command line option Message-ID: References: <20230605141332.25948-1-bp@alien8.de> <20230605141332.25948-2-bp@alien8.de> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230605141332.25948-2-bp@alien8.de> X-ClientProxiedBy: SJ0PR13CA0009.namprd13.prod.outlook.com (2603:10b6:a03:2c0::14) To SJ1PR11MB6201.namprd11.prod.outlook.com (2603:10b6:a03:45c::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PR11MB6201:EE_|DS7PR11MB6296:EE_ X-MS-Office365-Filtering-Correlation-Id: 135f14f9-12d2-489f-74af-08db67c3792a X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AZuIIfkYmwcXLfzN1Pzb+Yk1DQWrGUMwMj2iRDBqa0aoZRLfh8Fqcal+X8xtlgLU2CZoyllKOowDuSQU4Vz6fvNOhGz4uIARzww1/bz39mTlG0IpG0g4B5qH8REHX9PmsLgJe4TD/MroInWyqiLWGT8hjIVOBJoXVvj5+tm9XMtVyHApnB9VMPdKCVoptSqDVbp2ayTxa382s+zqBVs4pMUvJIq9hmvgSRAoqOoMeT0xjASV8R9RuIu0lJ9WBeik2r4cc2QEDXyvoSH9zxVu0Fq4bzfCFq3qpxd95vugL3d8wA++49INg1YdP8hBNTMY7zQlR0ZFo7FputIL8jNLY1y2knX5MqU7rbiPIuXNFOI1U9L97+tEyb6bS8j4T2V1SQlL+ekHNkgH8jk0aOPnaM/O19rT8kDu2St5CK5Bz8ATG9RHEavmsDH/1luQecO2aY0RAs++4fT+gArTKaPkvmerHWhhaJLyHGZV9CUvPYdl3FYIW4YjJZ7CxoCsWp22LMsL7Lkkgxfdv4cTixAmQoWm41HFvsIixo1NMeH9vO6eUqqmV1St3eYoHAaLtXLZ X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ1PR11MB6201.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(376002)(346002)(366004)(396003)(39860400002)(136003)(451199021)(107886003)(186003)(26005)(6506007)(6512007)(83380400001)(6486002)(6666004)(2906002)(8936002)(8676002)(82960400001)(54906003)(44832011)(478600001)(38100700002)(6916009)(41300700001)(86362001)(5660300002)(316002)(4326008)(66476007)(66556008)(66946007);DIR:OUT;SFP:1102; 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Add the first > chicken bit: to control whether the AMD side should load microcode late > on all logical SMT threads. > > Signed-off-by: Borislav Petkov (AMD) > --- > .../admin-guide/kernel-parameters.txt | 7 +++ > arch/x86/kernel/cpu/microcode/amd.c | 5 ++- > arch/x86/kernel/cpu/microcode/core.c | 44 +++++++++++++++++++ > arch/x86/kernel/cpu/microcode/internal.h | 16 +++++++ > 4 files changed, 71 insertions(+), 1 deletion(-) > create mode 100644 arch/x86/kernel/cpu/microcode/internal.h > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 9e5bab29685f..b88ff022402c 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -3228,6 +3228,13 @@ > > mga= [HW,DRM] > > + microcode= [X86] Control the behavior of the microcode > + loader. Available options: > + > + no_late_all - do not load on all SMT threads on > + AMD. Loading on all logical threads is enabled by > + default. > + The default behavior is that the reload happens on all threads for both early and late. The chicken bit in cmdline and the sysfs/control is to opt-out just in case they want to change the default behavior? When end user changes the behavior, isn't it against the design specification? And if so, should that result in kernel being tainted after a reload? Is this reload on all threads required by all models, or only certain models? I was wondering if the forced reload could be limited to only affected CPUs instead of doing it on all unconditionally. > min_addr=nn[KMG] [KNL,BOOT,IA-64] All physical memory below this > physical address is ignored. > > diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c > index 87208e46f7ed..76b530697951 100644 > --- a/arch/x86/kernel/cpu/microcode/amd.c > +++ b/arch/x86/kernel/cpu/microcode/amd.c > @@ -36,6 +36,8 @@ > #include > #include > > +#include "internal.h" > + > static struct equiv_cpu_table { > unsigned int num_entries; > struct equiv_cpu_entry *entry; > @@ -700,7 +702,8 @@ static enum ucode_state apply_microcode_amd(int cpu) > rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); > > /* need to apply patch? */ > - if (rev > mc_amd->hdr.patch_id) { > + if ((rev > mc_amd->hdr.patch_id) || > + (rev == mc_amd->hdr.patch_id && !(control & LATE_ALL_THREADS))) { > ret = UCODE_OK; > goto out; > } > diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c > index 3afcf3de0dd4..5f3185d2814c 100644 > --- a/arch/x86/kernel/cpu/microcode/core.c > +++ b/arch/x86/kernel/cpu/microcode/core.c > @@ -40,11 +40,15 @@ > #include > #include > > +#include "internal.h" > + > #define DRIVER_VERSION "2.2" > > static struct microcode_ops *microcode_ops; > static bool dis_ucode_ldr = true; > > +unsigned long control = LATE_ALL_THREADS; > + > bool initrd_gone; > > LIST_HEAD(microcode_cache); > @@ -522,8 +526,32 @@ static ssize_t processor_flags_show(struct device *dev, > return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); > } > > +static ssize_t control_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + return sprintf(buf, "0x%lx\n", control); > +} > + > +static ssize_t control_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t count) > +{ > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val) < 0) > + return -ERANGE; > + > + if (val & CONTROL_FLAGS_MASK) > + return -EINVAL; > + > + control = val; > + > + return count; > +} > + > static DEVICE_ATTR_RO(version); > static DEVICE_ATTR_RO(processor_flags); > +static DEVICE_ATTR_ADMIN_RW(control); > > static struct attribute *mc_default_attrs[] = { > &dev_attr_version.attr, > @@ -622,6 +650,7 @@ static struct attribute *cpu_root_microcode_attrs[] = { > #ifdef CONFIG_MICROCODE_LATE_LOADING > &dev_attr_reload.attr, > #endif > + &dev_attr_control.attr, Shouldn't the "control" be under LATE_LOADING? Since this only controls late-loading behavior?