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Message-ID: <38e5ffa2-93bd-ce70-ec00-6d61bad969c7@collabora.com>
Date:   Thu, 8 Jun 2023 10:53:47 +0200
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Subject: Re: [PATCH v2 4/5] clk: mediatek: mt8183: Add CLK_VDEC_ACTIVE to vdec
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To:     Chen-Yu Tsai <wenst@chromium.org>,
        =?UTF-8?B?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= 
        <nfraprado@collabora.com>
Cc:     Matthias Brugger <matthias.bgg@gmail.com>,
        Hans Verkuil <hverkuil-cisco@xs4all.nl>, kernel@collabora.com,
        Conor Dooley <conor+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Miles Chen <miles.chen@mediatek.com>,
        Rob Herring <robh+dt@kernel.org>,
        Stephen Boyd <sboyd@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org
References: <20230607205714.510012-1-nfraprado@collabora.com>
 <20230607205714.510012-5-nfraprado@collabora.com>
 <CAGXv+5EgP+0fTDhdpnYDCVQAWtWqwKp=Xxh-pHc1137wHoywRQ@mail.gmail.com>
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
In-Reply-To: <CAGXv+5EgP+0fTDhdpnYDCVQAWtWqwKp=Xxh-pHc1137wHoywRQ@mail.gmail.com>
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Il 08/06/23 09:43, Chen-Yu Tsai ha scritto:
> On Thu, Jun 8, 2023 at 4:57 AM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
>>
>> Add the CLK_VDEC_ACTIVE clock to the vdec clock driver. This clock is
>> enabled by the VPU once it starts decoding.
>>
>> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>>
>> ---
>>
>> Changes in v2:
>> - Added CLK_IGNORE_UNUSED flag
>>
>>   drivers/clk/mediatek/clk-mt8183-vdec.c | 5 +++++
>>   include/dt-bindings/clock/mt8183-clk.h | 3 ++-
>>   2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/clk-mt8183-vdec.c
>> index 513b7956cbea..03c4f1acfdb8 100644
>> --- a/drivers/clk/mediatek/clk-mt8183-vdec.c
>> +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c
>> @@ -27,6 +27,10 @@ static const struct mtk_gate_regs vdec1_cg_regs = {
>>          GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift,   \
>>                  &mtk_clk_gate_ops_setclr_inv)
>>
>> +#define GATE_VDEC0(_id, _name, _parent, _shift)                \
>> +       GATE_MTK_FLAGS(_id, _name, _parent, &vdec0_cg_regs, _shift,     \
>> +               &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED)
> 
> I think what you want is a read-only gate clock only used for reading back
> the status. The ops would only have .is_enabled.

Technically, you're right... but I would delay the introduction of a RO GATE_MTK
clock for later, as it's not worth adding that for just one clock driver usage.

We're checking if the same can be applied to other SoCs as well - if it can,
then it would make sense to do that (small, yes), work... the point here is to
enable MT8183 decoders ASAP to enable decoder tests in KernelCI, along with
all of the other MediaTek Chromebooks.

Though, if you think that it is a good idea to add a RO gate right now, I don't
have any strong opinions against that.

Cheers,
Angelo