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From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Thu, 8 Jun 2023 11:58:36 +0200
Message-ID: <CAMuHMdVFBo+KMNQ6gzh3rZrZ+_Wfg=UJ4XOW4Uqibnjm6T7CdA@mail.gmail.com>
Subject: Re: [PATCH v2 3/3] sh: dma: Correct the number of DMA channels in SH7709
To:     John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Cc:     Artur Rojek <contact@artur-rojek.eu>,
        Yoshinori Sato <ysato@users.sourceforge.jp>,
        Rich Felker <dalias@libc.org>,
        Rafael Ignacio Zurita <rafaelignacio.zurita@gmail.com>,
        linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org
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Hi Adrian,

On Thu, Jun 8, 2023 at 11:54 AM John Paul Adrian Glaubitz
<glaubitz@physik.fu-berlin.de> wrote:
> On Wed, 2023-06-07 at 11:16 +0200, Geert Uytterhoeven wrote:
> > On Sat, May 27, 2023 at 6:45 PM Artur Rojek <contact@artur-rojek.eu> wrote:
> > > According to the hardware manual [1], the DMAC found in SH7709 features
> > > only 4 channels.
> > >
> > > While at it, also sort the existing targets and clarify that
> > > NR_ONCHIP_DMA_CHANNELS must be a multiply of two.
> > >
> > > [1] https://www.renesas.com/us/en/document/mah/sh7709s-group-hardware-manual (p. 373)
> > >
> > > Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
> > > ---
> > >
> > > v2: - sort existing targets
> >
> > Thanks for the update!
> >
> > >     - clarify that the value must be a multiply of two
> >
> > That's only true when there are two DMACs, right?
> >
> > Even in that case, you could mitigate that by avoiding the division by
> >
> >     #ifdef SH_DMAC_BASE1
> >    -#define        SH_DMAC_NR_MD_CH        (CONFIG_NR_ONCHIP_DMA_CHANNELS / 2)
> >    +#define        SH_DMAC_NR_MD_CH        6
> >     #else
> >     #define        SH_DMAC_NR_MD_CH        CONFIG_NR_ONCHIP_DMA_CHANNELS
> >     #endif
>
> Aren't we dropping SH_DMAC_BASE1 in the other patch anyway?

Only for the SH4 parts that do not have it.
It is still set in arch/sh/include/cpu-sh4a/cpu/dma.h for the SH4a parts with
12 channels and 2 DMACs.

> > That is actually safer, as the user can override NR_ONCHIP_DMA_CHANNELS
> > when configuring his kernel, thus breaking DMA  due to an incorrect
> > value of SH_DMAC_NR_MD_CH.
> >
> > Unfortunately we cannot protect against that when using a single DMAC,
> > as SH_DMAC_NR_MD_CH can be either 4, 6, or 8.
> >
> > Perhaps this configuration should be moved from Kconfig to <cpu/dma.h>,
> > to protect against a user overriding this value?
>
> Isn't SH_DMAC_NR_MD_CH already hardwired to the SoC being used?

It depends on CONFIG_NR_ONCHIP_DMA_CHANNELS, while it
should be fixed based on the SoC.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds