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Message-ID: <8205bc2cb9f983914ff6920deed3f54893713ba0.camel@physik.fu-berlin.de>
Subject: Re: [PATCH v2 3/3] sh: dma: Correct the number of DMA channels in
 SH7709
From:   John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Artur Rojek <contact@artur-rojek.eu>,
        Yoshinori Sato <ysato@users.sourceforge.jp>,
        Rich Felker <dalias@libc.org>,
        Rafael Ignacio Zurita <rafaelignacio.zurita@gmail.com>,
        linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org
Date:   Thu, 08 Jun 2023 12:03:43 +0200
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Hi Geert!

On Thu, 2023-06-08 at 11:58 +0200, Geert Uytterhoeven wrote:
> > 
> > Aren't we dropping SH_DMAC_BASE1 in the other patch anyway?
> 
> Only for the SH4 parts that do not have it.
> It is still set in arch/sh/include/cpu-sh4a/cpu/dma.h for the SH4a parts with
> 12 channels and 2 DMACs.

OK, thanks for the clarification. I will review the other patches tonight.

> > > That is actually safer, as the user can override NR_ONCHIP_DMA_CHANNELS
> > > when configuring his kernel, thus breaking DMA  due to an incorrect
> > > value of SH_DMAC_NR_MD_CH.
> > > 
> > > Unfortunately we cannot protect against that when using a single DMAC,
> > > as SH_DMAC_NR_MD_CH can be either 4, 6, or 8.
> > > 
> > > Perhaps this configuration should be moved from Kconfig to <cpu/dma.h>,
> > > to protect against a user overriding this value?
> > 
> > Isn't SH_DMAC_NR_MD_CH already hardwired to the SoC being used?
> 
> It depends on CONFIG_NR_ONCHIP_DMA_CHANNELS, while it
> should be fixed based on the SoC.

I agree. However, I would be fine with merging this patch set first and fixing
this particular issue in a follow-up series.

Adrian

-- 
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer
`. `'   Physicist
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