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Date:   Thu, 8 Jun 2023 14:32:44 +0300
From:   Dmitry Rokosov <ddrokosov@sberdevices.ru>
To:     Jerome Brunet <jbrunet@baylibre.com>
CC:     Yu Tu <yu.tu@amlogic.com>, <linux-clk@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-amlogic@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Kevin Hilman <khilman@baylibre.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        <kelvin.zhang@amlogic.com>, <qi.duan@amlogic.com>
Subject: Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC
 PLL clock driver
Message-ID: <20230608113244.jvf7w4flwjy5soud@CAB-WSD-L081021>
References: <20230517070215.28463-1-yu.tu@amlogic.com>
 <20230517070215.28463-4-yu.tu@amlogic.com>
 <1j5y804q7u.fsf@starbuckisacylon.baylibre.com>
 <73acf297-3f60-1ce1-2f05-af048aa37199@amlogic.com>
 <1jttvi9vnq.fsf@starbuckisacylon.baylibre.com>
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Hello Jerome,

On Thu, Jun 08, 2023 at 10:53:31AM +0200, Jerome Brunet wrote:
> 
> >>> +
> >>> +static struct clk_regmap s4_fclk_div4 = {
> >>> +     .data = &(struct clk_regmap_gate_data){
> >>> +             .offset = ANACTRL_FIXPLL_CTRL1,
> >>> +             .bit_idx = 21,
> >>> +     },
> >>> +     .hw.init = &(struct clk_init_data){
> >>> +             .name = "fclk_div4",
> >>> +             /*
> >>> +              * For more information, please refer to s4_fixed_pll_dco.
> >>> +              */
> >> While div2 and div3 got an explanation from previous SoCs, they others -
> >> like div4/div7/etc ... - have been able to cope with rw ops so far.
> >> Why is the S4 different for all these clocks ?
> >
> > The chip was changed fixed pll for security reasons.
> >
> > Fixed PLL registers are not writable in the kernel phase. Write of fixed
> > PLL-related register will cause the system to crash.
> >
> 
> That is definitely worth mentionning
> 
> >> Requiring RO ops (or fishy clock flags) is usually a sign that a clock
> >> is used without an appropriate driver.
> >>
> 
> Neil is currently dealing with the dt-bindings, please
> * Adjust your patchset accordingly
> * Wait for his v2 to land, you'll need it.
> 

I saw Neil patch series with merging 'private' and 'public' clock
bindings parts. Should I send the same patchset for a1 clocks after v6.5
landed?

> >>> +             .ops = &clk_regmap_gate_ro_ops,
> >>> +             .parent_hws = (const struct clk_hw *[]) {
> >>> +                     &s4_fclk_div4_div.hw
> >>> +             },
> >>> +             .num_parents = 1,
> >>> +     },
> >>> +};
> >>> +
> 
> _______________________________________________
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> http://lists.infradead.org/mailman/listinfo/linux-amlogic

-- 
Thank you,
Dmitry