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bh=SevHFuFvWiWBIFRswg9uj8IfEdbzTFJ6Jca5wyhSDJw=; b=cI52B7dQFtgtOpW3bCdq0HVkE/XgLNRXmBW9phse3D0ARiqBxdnA/0qUmiygJNECj2 KateqieNPoXnlxs41bW9LBntGOxnSw3PPnJEL1mAJkHbTlWyiHWJ1qiJhVc4dsdJjTij zIF8mTvhs5XY+VrJWwt3f5b7m82QDU+tIHA+S27vFaIABp2JIylhaeU6Wtm2ODpFN5gx IC8/aP8vOW6QIG0W2npZU/IjUUB8bBCcRWSl2KlUK5sNEeDNniMtoots/ZxsN3Ro3JqT LonSSyhvAnh4UiD79CcziVc7GhLtHZJ9dWZay4OuWA8YfBZsg8+c0EkDguU4KIkGrKV1 znUw== X-Gm-Message-State: AC+VfDwgi9oQp11H3xw21HYzyKi2MWdJqgSvVSRTiyyDoghXSckbMaVo QPmjmzguHDElsC4GmRzHtclrj1Z/ttBSjsu+ty9PsA== X-Received: by 2002:a81:92cc:0:b0:561:cb45:d7de with SMTP id j195-20020a8192cc000000b00561cb45d7demr987980ywg.31.1686264496190; Thu, 08 Jun 2023 15:48:16 -0700 (PDT) MIME-Version: 1.0 References: <20230601015115.406002-1-victorshihgli@gmail.com> <20230601015115.406002-3-victorshihgli@gmail.com> In-Reply-To: <20230601015115.406002-3-victorshihgli@gmail.com> From: Ulf Hansson Date: Fri, 9 Jun 2023 00:47:40 +0200 Message-ID: Subject: Re: [PATCH V5 2/4] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767 To: Victor Shih Cc: adrian.hunter@intel.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, Ben Chuang , Victor Shih Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 1 Jun 2023 at 03:51, Victor Shih wrote: > > From: Victor Shih > > Set GL9767 SDR104's clock to 205MHz and enable SSC feature > depend on register 0x888 BIT(1). > > Signed-off-by: Ben Chuang > Signed-off-by: Victor Shih > Acked-by: Adrian Hunter > --- > drivers/mmc/host/sdhci-pci-gli.c | 135 ++++++++++++++++++++++++++++++- [...] > + > +static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) > +{ > + u32 pll; > + > + gl9767_vhs_write(pdev); > + > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); > + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV | > + PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV | > + PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN); > + pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) | > + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) | > + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir); > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); > + > + gl9767_vhs_read(pdev); > + > + /* wait for pll stable */ > + msleep(1); According to Documentation/timers/timers-howto.rst, this should be converted into usleep_range instead. [...] Other than the minor thing above, this looks good to me! Kind regards Uffe