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References: <20230607090653.2468317-1-wenst@chromium.org> <20230607090653.2468317-5-wenst@chromium.org>
 <b61c7d8c-85e7-2248-d386-ffec8c275aa4@collabora.com>
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From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Fri, 9 Jun 2023 14:54:08 +0800
Message-ID: <CAGXv+5Gi1B0FzVtA4ZoQ7Ra+JOZWh68mQTi+G4Y2NBe+t9ehiA@mail.gmail.com>
Subject: Re: [PATCH 4/4] arm64: dts: mediatek: mt8186: Wire up GPU
 voltage/frequency scaling
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     Matthias Brugger <matthias.bgg@gmail.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
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On Thu, Jun 8, 2023 at 8:14=E2=80=AFPM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 07/06/23 11:06, Chen-Yu Tsai ha scritto:
> > Add the GPU's OPP table. This is from the downstream ChromeOS kernel,
> > adapted to the new upstream opp-supported-hw binning format. Also add
> > dynamic-power-coefficient for the GPU.
> >
> > Also add label for mfg1 power domain. This is to be used at the board
> > level to add a regulator supply for the power domain.
> >
> > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++=
-
> >   1 file changed, 139 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot=
/dts/mediatek/mt8186.dtsi
> > index c58d7eb87b1d..a34489e27cd4 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -695,6 +695,142 @@ clk32k: oscillator-32k {
> >               clock-output-names =3D "clk32k";
> >       };
> >
> > +     gpu_opp_table: opp-table-gpu {
> > +             compatible =3D "operating-points-v2";
> > +
> > +             opp-299000000 {
> > +                     opp-hz =3D /bits/ 64 <299000000>;
> > +                     opp-microvolt =3D <612500>;
> > +                     opp-supported-hw =3D <0x38>;
>
> For all of the OPPs that are supposed to be supported by all speed-bins, =
you don't
> need to restrict them to all "known" bins.
>
> Please change opp-supported-hw from <0x38> to <0xff>, which literally mea=
ns
> just "applies to all revisions".

OK.

> > +             };
>
>
> ..snip...
>
> > +
> > +             opp-900000000-3 {
>
> What about calling those like "opp-900000000-bin3"?
> Makes it clear that it's tied to what MediaTek calls a speedbin "3" (as w=
e're
> interpreting the values in the nvmem driver to make them compatible with =
the
> opp-supported-hw's expectations).

I thought that at first as well, but the bindings require the OPP node to
be named following '^opp(-?[0-9]+)*$':, so numbers only.

ChenYu